Non-binary rank multiplication of memory module

1. A system, comprising:

a memory controller;

a processor;

a non-transitory computer readable medium including instructions executable by the processor to repurpose a chip select input of a plurality of chip select inputs of a load-reduced dual inline memory module (LRDIMM) to an address input, and reroute the address input of the repurposed chip select input to a plurality of memory ranks of the LRDIMM to support non-binary rank multiplication of the LRDIMM, wherein the LRDIMM is to present a number of logical ranks to the memory controller, and the non-binary rank multiplication comprises the non-binary rank multiplication of the number of logical ranks to provide the plurality of memory ranks of the LRDIMM; and

a buffer to map a selected logical rank of the number of logical ranks as selected by the memory controller using the plurality of chip select inputs, to a selected memory rank of the plurality of memory ranks, the selected memory rank selected based on selection using an address provided by the memory controller and a remainder of the plurality of chip select inputs other than the repurposed chip select input, wherein the buffer is to be set to a binary rank multiplication number greater than a non-binary rank multiplication supported by the LRDIMM and larger than a number of the plurality of memory ranks of the LRDIMM, wherein the non-binary rank multiplication is associated with a non-binary rank number of the plurality of memory ranks.

2. The system of claim 1 , wherein,

the LRDIMM includes a plurality of address inputs, and

the instructions are to select the selected memory rank of the plurality of memory ranks of the LRDIMM based on at least one of the plurality of address inputs.

3. The system of claim 2 , wherein,

each of the plurality of address inputs relates to a separate bit of an address, and

the repurposed chip select input adds a most significant bit to the address of the plurality of address inputs.

4. The system of claim 3 , further comprising:

a plurality of LRDIMMs per channel; and

each of the plurality of LRDIMMs is to present multiple logical ranks to the memory controller, and

the memory controller is to provide a different address range for each of the logical ranks that are selected.

5. The system of claim 1 , wherein the LRDIMM includes a double data rate (DDR) memory.

6. The system of claim 1 , wherein,

the instructions are to route a memory rank indicated by the buffer that is not included in the LRDIMM to one of the plurality of memory ranks of the LRDIMM.

7. The system of claim 1 , wherein the non-binary rank multiplication comprises one of 3×, 5×, 6× or 7× rank multiplication, and wherein the LRDIMM is to support one of 6, 10, 12, or 14 memory ranks.

8. A method, comprising:

receiving, at a load-reduced dual inline memory module (LRDIMM), a plurality of chip select inputs from a memory controller, wherein the LRDIMM is to present a number of logical ranks to the memory controller;

repurposing, at the LRDIMM, a chip select input of the plurality of chip select inputs to be an address input of an address range, wherein the address input of the repurposed chip select input is rerouted to a plurality of memory ranks of the LRDIMM, the repurposed chip select input supporting non-binary rank multiplication of the LRDIMM, and the non-binary rank multiplication comprises the non-binary rank multiplication of the number of logical ranks to produce a quantity of the plurality of memory ranks of the LRDIMM; and

selecting a selected memory rank of the plurality of memory ranks based on a remainder of the chip select inputs other than the repurposed chip select input, the selecting comprising mapping, using a buffer, a selected logical rank of the number of logical ranks as selected by the memory controller using the plurality of chip select inputs, to the selected memory rank of the plurality of memory ranks, wherein the buffer is set to a binary rank multiplication number greater than the non-binary rank multiplication supported by the LRDIMM and larger than the quantity of the plurality of memory ranks of the LRDIMM, wherein the non-binary rank multiplication is associated with a non-binary rank number of the plurality of memory ranks.

9. The method of claim 8 , wherein the selecting further includes selecting the selected memory rank further based on at least a portion of the address range.

10. The method of claim 9 , wherein,

the address range is based on a plurality of address inputs, each address input being a bit of the address range, and

the repurposed chip select input is repurposed to be a most significant bit of the address range.

11. The method of claim 9 , wherein,

the memory controller is to output the address range to the LRDIMM and to output a chip selection via the plurality of chip select inputs, the chip selection to select the selected logical rank of the number of logical ranks viewable by the memory controller at the LRDIMM.

12. The method of claim 8 , wherein,

the non-binary rank multiplication includes one of 3×, 5×, 6×, or 7× rank multiplication, and

the LRDIMM is to support one of 6, 10, 12, or 14 memory ranks.

13. A system comprising:

a memory controller; and

a load-reduced dual inline memory module (LRDIMM) comprising a processor to:

repurpose a chip select input of a plurality of chip select inputs to be an address input of a plurality of address inputs at the LRDIMM, wherein the LRDIMM is to present a number of logical ranks to the memory controller, the repurposed chip select input supporting non-binary rank multiplication of the LRDIMM, and the non-binary rank multiplication comprises the non-binary rank multiplication of the number of logical ranks to produce a quantity of a plurality of memory ranks of the LRDIMM; and

select a selected memory rank of the plurality of memory ranks of the LRDIMM based on the plurality of chip select inputs, the LRDIMM comprising a buffer to map a selected logical rank of the number of logical ranks as selected by the memory controller using the plurality of chip select inputs, to the selected memory rank of the plurality of memory ranks, wherein the buffer is set to a binary rank multiplication number of a buffer to be greater than the non-binary rank multiplication supported by the LRDIMM and larger than the quantity of the plurality of memory ranks of the LRDIMM, wherein the non-binary rank multiplication is associated with a non-binary rank number of the plurality of memory ranks.

14. The system of claim 13 , wherein:

the non-binary rank multiplication includes one of 3×, 5×, 6×, or 7× rank multiplication, and

the LRDIMM is to support one of 6, 10, 12, or 14 memory ranks.

15. The system of claim 13 , wherein the LRDIMM is to route a memory rank indicated by the buffer that is not included in the LRDIMM to one of the plurality of memory ranks of the LRDIMM.

16. The system of claim 13 , wherein,

each of the plurality of address inputs relates to a separate bit of an address, and

the repurposed chip select input is to add a most significant bit to the address.

17. The system of claim 1 , comprising the LRDIMM, wherein the processor, the non-transitory computer readable medium, and the buffer are part of the LRDIMM.

18. The method of claim 8 , further comprising:

routing a memory rank indicated by the buffer that is not included in the LRDIMM to one of the plurality of memory ranks of the LRDIMM.

19. The method of claim 8 , wherein each of a plurality of LRDIMMs is to present multiple logical ranks to the memory controller, and the memory controller selects a logical rank of one of the plurality of LRDIMMs.