Buffer chip, semiconductor package including buffer chip and memory chip, and memory module
A buffer chip may include: a chip select signal reception circuit configured to receive system chip select signals transmitted from a memory controller; a chip select signal mapping circuit configured to generate memory chip select signals by mapping the system chip select signals by using failed memory chip information; and a chip select signal transmission circuit configured to transmit the memory chip select signals to a plurality of memory chips.
1 . A buffer chip comprising:
a chip select signal reception circuit configured to receive system chip select signals transmitted from a memory controller;
a chip select signal mapping circuit configured to generate memory chip select signals by mapping the system chip select signals by using failed memory chip information;
a chip select signal transmission circuit configured to transmit the memory chip select signals to a plurality of memory chips;
a reset signal reception circuit configured to receive a system reset signal transferred from the memory controller;
a reset signal generation circuit configured to generate memory reset signals corresponding to the plurality of memory chips by using the failed memory chip information and the system reset signal; and
a reset signal transmission circuit configured to transmit the memory reset signals to the plurality of memory chips.
2 . The buffer chip of claim 1 , wherein the chip select signal mapping circuit is configured to remap initial ranks of the plurality of memory chips so that at least one rank includes memory chips that are all passed memory chips when all initial ranks include at least one failed memory chip.
3 . A buffer chip comprising:
a chip select signal reception circuit configured to receive system chip select signals transmitted from a memory controller;
a chip select signal mapping circuit configured to generate memory chip select signals by mapping the system chip select signals by using failed memory chip information; and
a chip select signal transmission circuit configured to transmit the memory chip select signals to a plurality of memory chips,
wherein the number of memory chips is N (N is an integer of 2 or more), the number of system chip select signals is N, and the number of memory chip select signals is N,
wherein K number of the memory chips (K is an integer of 0 or more and less than N) are failed memory chips, and
wherein the chip select signal mapping circuit is configured to fix K memory chip select signals corresponding to the K failed memory chips to a deactivated state and configured to generate remaining (N−K) memory chip select signals to have the same level as (N−K) system chip select signals, among the N system chip select signals.
4 . The buffer chip of claim 1 , wherein the reset signal generation circuit is configured to fix a memory reset signal corresponding to a failed memory chip, among the memory reset signals to an activated state.
5 . The buffer chip of claim 1 , further comprising:
a command address reception circuit configured to receive command address signals transferred from the memory controller;
a command address transmission circuit configured to transmit the command address signals to the plurality of memory chips;
an external data interface configured to transmit and receive data to and from the memory controller; and
an internal data interface configured to transmit and receive the data to and from the plurality of memory chips.
6 . The buffer chip of claim 5 , further comprising:
a control signal transmission circuit configured to transmit the memory chip select signals generated by the chip select signal mapping circuit and the command address signals received through the command address reception circuit to the chip select signal transmission circuit and the command address transmission circuit;
a command decoder configured to decode the command address signals and the memory chip select signals;
a setting circuit configured to perform a setting operation according to a decoding result of the command decoder;
a latency control circuit configured to control an activation and a deactivation of the external data interface and the internal data interface during a write operation and a read operation;
a clock reception circuit configured to receive a clock from the memory controller;
a clock transmission circuit configured to transmit the clock received by the clock reception circuit to the plurality of memory chips; and
a fail information storage circuit configured to store the failed memory chip information.
7 . A memory module comprising:
a module controller including a host interface for communication with a host, a memory controller logic for memory control, and a memory interface for transmission of control signals and transmission and reception of data; and
a plurality of semiconductor packages connected to the module controller,
wherein each of the plurality of semiconductor packages comprises:
a buffer chip receiving the control signals from the memory interface and transmitting and receiving the data to and from the memory interface; and
a plurality of memory chips receiving the control signals through the buffer chip and transmitting and receiving the data through the buffer chip, and the buffer chip comprises:
a chip select signal reception circuit configured to receive system chip select signals included in the control signals;
a chip select signal mapping circuit configured to generate memory chip select signals by mapping the system chip select signals by using failed memory chip information;
a chip select signal transmission circuit configured to transmit the memory chip select signals to a plurality of memory chips;
a reset signal reception circuit configured to receive a system reset signal transferred from the memory controller;
a reset signal generation circuit configured to generate memory reset signals corresponding to the plurality of memory chips by using the failed memory chip information and the system reset signal; and
a reset signal transmission circuit configured to transmit the memory reset signals to the plurality of memory chips.
8 . A memory module comprising:
a module controller including a host interface for communication with a host, a memory controller logic for memory control, and a memory interface for transmission of control signals and transmission and reception of data; and
a plurality of semiconductor packages connected to the module controller,
wherein each of the plurality of semiconductor packages comprises:
a buffer chip receiving the control signals from the memory interface and transmitting and receiving the data to and from the memory interface; and
a plurality of memory chips receiving the control signals through the buffer chip and transmitting and receiving the data through the buffer chip, and
the buffer chip comprises:
a chip select signal reception circuit configured to receive system chip select signals included in the control signals;
a chip select signal mapping circuit configured to generate memory chip select signals by mapping the system chip select signals by using failed memory chip information; and
a chip select signal transmission circuit configured to transmit the memory chip select signals to a plurality of memory chips,
wherein the chip select signal mapping circuit is configured to remap initial ranks of the plurality of semiconductor packages so that at least one rank includes memory chips that are all passed memory chips when all initial ranks of the plurality of semiconductor packages include at least one failed memory chip.
9 . The memory module of claim 7 , wherein the chip select signal mapping circuit is configured to fix a memory chip select signal corresponding to a failed memory chip among the memory chip select signals to a deactivated state.
10 . The memory module of claim 9 , wherein the reset signal generation circuit is configured to fix a memory reset signal corresponding to a failed memory chip among the memory reset signals to an activated state.
11 . The memory module of claim 7 , wherein chip select signal mapping circuits of buffer chips in the plurality of semiconductor chips are configured to perform the mapping operation so that memory chips corresponding to the same system chip select signal in all the semiconductor packages are processed to be failed memory chips.
12 . A semiconductor package comprising:
a package substrate including a plurality of terminals to communicate with a memory controller and a plurality of bonding pads to communicate inside a package;
a buffer chip stacked on the package substrate;
a plurality of memory chips stacked on the buffer chip; and
a plurality of wires connecting the plurality of bonding pads and the plurality of memory chips,
wherein the buffer chip communicates with the memory controller through the plurality of terminals of the package substrate,
the plurality of memory chips communicate with the buffer chip through the plurality of wires and the plurality of bonding pads of the package substrate, and
the buffer chip comprises:
a chip select signal reception circuit configured to receive system chip select signals transmitted from a memory controller;
a chip select signal mapping circuit configured to generate memory chip select signals by mapping the system chip select signals by using failed memory chip information; and
a chip select signal transmission circuit configured to transmit the memory chip select signals to a plurality of memory chips.
13 . The semiconductor package of claim 12 , wherein the buffer chip further comprises:
a reset signal reception circuit configured to receive a system reset signal transferred from the memory controller;
a reset signal generation circuit configured to generate memory reset signals corresponding to the plurality of memory chips by using the failed memory chip information and the system reset signal; and
a reset signal transmission circuit configured to transmit the memory reset signals to the plurality of memory chips.
14 . The semiconductor package of claim 12 , wherein the chip select signal mapping circuit is configured to remap initial ranks of the plurality of memory chips so that at least one rank includes memory chips that are all passed memory chips when all initial ranks include at least one failed memory chip.
15 . The semiconductor package of claim 12 , wherein the number of memory chips is N (N is an integer of 2 or more), the number of system chip select signals is N, the number of memory chip select signals is N, K of the memory chips (K is an integer of 0 or more and less than N) are failed memory chips, and
wherein the chip select signal mapping circuit is configured to fix K memory chip select signals corresponding to the K failed memory chips to a deactivated state, and generates remaining (N−K) memory chip select signals to have the same level as (N−K) system chip select signals among the N system chip select signals.
16 . The semiconductor package of claim 13 , wherein the reset signal generation circuit is configured to fix a memory reset signal corresponding to a failed memory chip among the memory reset signals to an activated state.
17 . The semiconductor package of claim 15 , wherein the buffer chip further comprises:
a command address reception circuit configured to receive command address signals transferred from the memory controller;
a command address transmission circuit configured to transmit the command address signals to the plurality of memory chips;
an external data interface configured to transmit and receive data to and from the memory controller; and
an internal data interface configured to transmit and receive the data to and from the plurality of memory chips.
18 . The semiconductor package of claim 17 , wherein the buffer chip further comprises:
a control signal transmission circuit configured to transmit the memory chip select signals generated by the chip select signal mapping circuit and the command address signals received through the command address reception circuit to the chip select signal transmission circuit and the command address transmission circuit;
a command decoder configured to decode the command address signals and the memory chip select signals;
a setting circuit configured to perform a setting operation according to a decoding result of the command decoder;
a latency control circuit configured to control activation and deactivation of the external data interface and the internal data interface during a write operation and a read operation;
a clock reception circuit configured to receive a clock from the memory controller;
a clock transmission circuit configured to transmit the clock received by the clock reception circuit to the plurality of memory chips; and
a fail information storage circuit configured to store the failed memory chip information.