Buffer chip, semiconductor package including buffer chip and memory chip, and memory module
A buffer chip includes: an external control signal interface configured to receive control signals transmitted from a memory controller; an internal control signal interface configured to transmit the control signals to a plurality of memory chips; an external data interface configured to transmit and receive (transmit/receive) data to and from (to/from) the memory controller; an internal data interface configured to transmit/receive the data to/from the plurality of memory chips; and a loopback circuit configured to be activated in a loopback mode to receive the control signals transmitted by the internal control signal interface, and transmits the control signals to the external data interface.
1 . A buffer chip comprising:
an external control signal interface configured to receive control signals transmitted from a memory controller;
an internal control signal interface configured to transmit the control signals to a plurality of memory chips;
an external data interface configured to transmit and receive (transmit/receive) data to and from (to/from) the memory controller;
an internal data interface configured to transmit/receive the data to/from the plurality of memory chips; and
a loopback circuit configured to be activated in a loopback mode to receive the control signals transmitted by the internal control signal interface, and to transmit the control signals to the external data interface.
2 . The buffer chip of claim 1 , wherein, in the loopback mode, the external data interface transmits the control signals transmitted from the loopback circuit to the memory controller.
3 . The buffer chip of claim 2 , wherein the loopback circuit comprises:
a loopback reception circuit configured to receive the control signals transmitted by the internal control signal interface;
a loopback selection circuit configured to select a part of the control signals received by the loopback reception circuit; and
a mode control circuit configured to transmit the control signals selected by the loopback selection circuit to the external data interface during activation of a loopback mode signal, and to transmit the data received by the internal data interface to the external data interface during deactivation of the loopback mode signal.
4 . The buffer chip of claim 1 , further comprising:
a control signal transmission circuit configured to buffer the control signals received through the external control signal interface and to transmit the buffered control signals to the internal control signal interface;
a command decoder configured to decode the control signals received through the external control signal interface;
a setting circuit configured to perform a setting operation according to a decoding result of the command decoder and to control the setting of the loopback mode;
a latency control circuit configured to control activation and deactivation of the external data interface and the internal data interface during a write operation and a read operation, and to activate the external data interface in the loopback mode;
a clock reception circuit configured to receive a clock from the memory controller;
a clock transmission circuit configured to transmit the clock received by the clock reception circuit to the plurality of memory chips;
an external alert signal interface configured to transmit/receive an alert signal to/from the memory controller; and
an internal alert signal interface configured to transmit/receive the alert signal to/from the memory chips.
5 . The buffer chip of claim 4 , wherein the loopback circuit comprises:
a loopback reception circuit configured to receive the control signals transmitted by the internal control signal interface, the clock transmitted by the clock transmission circuit, and the alert signal transmitted by the internal alert signal interface;
a loopback selection circuit configured to select a part of the signals received by the loopback reception circuit; and
a mode control circuit configured to transmit the signals selected by the loopback selection circuit to the external data interface during activation of a loopback mode signal, and to transmit the data received by the internal data interface to the external data interface during deactivation of the loopback mode signal.
6 . The buffer chip of claim 5 , wherein the loopback circuit further comprises:
a reference voltage generation circuit configured to generate reference voltages to be used by the loopback reception circuit.
7 . The buffer chip of claim 1 , wherein the control signals include chip select signals and command address signals.
8 . A semiconductor package comprising:
a package substrate including a plurality of terminals configured to communicate with a memory controller and a plurality of bonding pads configured to communicate inside a package;
a buffer chip disposed on the package substrate;
a plurality of memory chips stacked on the buffer chip; and
a plurality of wires connecting the plurality of bonding pads and the plurality of memory chips,
wherein the buffer chip communicates with the memory controller through the plurality of terminals of the package substrate,
wherein the plurality of memory chips communicate with the buffer chip through the plurality of wires and the plurality of bonding pads of the package substrate, and
wherein the buffer chip comprises:
an external control signal interface configured to receive control signals transmitted from the memory controller;
an internal control signal interface configured to transmit the control signals to the plurality of memory chips;
an external data interface configured to transmit and receive (transmit/receive) data to and from (to/from) the memory controller;
an internal data interface for configured to transmit/receive the data to/from the plurality of memory chips; and
a loopback circuit configured to be activated in a loopback mode to receive the control signals transmitted by the internal control signal interface, and to transmit the control signals to the external data interface.
9 . The semiconductor package of claim 8 , wherein, in the loopback mode, the external data interface transmits the control signals transmitted from the loopback circuit to the memory controller.
10 . A memory module comprising:
a module controller including a host interface for communication with a host, a memory controller logic for memory control, and a memory interface for transmission of control signals and the transmission and reception (transmission/reception) of data;
a buffer chip configured to receive the control signals from the memory interface and to transmit and receive (transmit/receive) the data to and from (to/from) the memory interface; and
a plurality of memory chips configured to receive the control signals through the buffer chip and to transmit/receive the data through the buffer chip,
wherein the buffer chip comprises:
an external control signal interface configured to receive control signals transmitted from the memory controller;
an internal control signal interface configured to transmit the control signals to the plurality of memory chips;
an external data interface configured to transmit/receive data to/from the memory controller;
an internal data interface for configured to transmit/receive the data to/from the plurality of memory chips; and
a loopback circuit configured to be activated in a loopback mode to receive the control signals transmitted by the internal control signal interface, and to transmit the control signals to the external data interface.
11 . The memory module of claim 10 , wherein the loopback circuit comprises:
a loopback reception circuit configured to receive the control signals transmitted by the internal control signal interface;
a loopback selection circuit configured to select a part of the control signals received by the loopback reception circuit; and
a mode control circuit configured to transmit the control signals selected by the loopback selection circuit to the external data interface during activation of a loopback mode signal, and to transmit the data received by the internal data interface to the external data interface during deactivation of the loopback mode signal.