Memory module

1. A memory module, comprising:

a plurality of first memory ranks that share a first chip select signal and have different chip IDs;

a plurality of second memory ranks that share a second chip select signal and have different chip IDs; and

a rank mapping circuit suitable for mapping a defective first memory rank among the first memory ranks to a defect-free second memory rank among the second memory ranks by mapping the first chip select signal to the second chip select signal and changing a chip ID of the defective first memory rank.

2. The memory module of claim 1 ,

wherein a supply of a clock toward the defective first memory rank among the first memory ranks is blocked off, and

wherein the supply of the clock toward a defective second memory rank among the second memory ranks is blocked off.

3. The memory module of claim 2 , further comprising:

a plurality of clock gating circuits suitable for controlling the supply of the clock toward the first memory ranks and the second memory ranks.

4. The memory module of claim 1 , wherein a supply of the clock toward a defective second memory rank and second memory ranks that are not used for the mapping among the second memory ranks is blocked off.

5. The memory module of claim 1 , further comprising:

a Serial Presence Detect (SPD) suitable for providing a memory controller with information representing that a total capacity of the memory module is equal to a total capacity of the first group.

6. The memory module of claim 1 , wherein the rank mapping circuit is included in a module controller, and

the module controller includes:

an error correction code generation circuit suitable for generating an error correction code which is to be stored together with a write data which is to be programmed in the first group and the second group based on the write data which is to be programmed in the first group and the second group; and

an error correction circuit suitable for correcting an error of a read data which is read from the first group and the second group based on the error correction code which is read from the first group and the second group.

7. The memory module of claim 6 , wherein the module controller further includes:

a command buffer circuit suitable for buffering a command which is to be transferred to the first group and the second group; and

an address buffer circuit suitable for buffering an address which is to be transferred to the first group and the second group.

8. The memory module of claim 6 , further comprising:

a plurality of data buffers suitable for receiving a write data transferred from a memory controller and transferring the received write data to the module controller, and receiving a read data transferred from the module controller and transferring the received read data to the memory controller.

9. The memory module of claim 1 , wherein each of the first memory ranks and the second memory ranks includes a plurality of memory devices.

10. The memory module of claim 9 , wherein each of the memory devices is a Dynamic Random-Access Memory (DRAM), and

the memory module is of a Dual In-Line Memory Module (DIMM).