Subgroup selection for verification
An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.
1. An apparatus comprising:
a plurality of memory cells;
a state change circuit configured to alter a data state of each of the memory cells configured to be programmed;
a determination circuit configured to determine a relative rate of state change for at least two subgroups of memory cells; and
an identification circuit configured to identify a subgroup of memory cells that satisfies a state change characteristic based on the relative rate of state change.
2. The apparatus of claim 1 , wherein the identified subgroup of memory cells that satisfies the state change characteristic comprises at least one of:
a fastest subgroup of memory cells; and
a slowest subgroup of memory cells.
3. The apparatus of claim 2 , wherein:
the data state of each of the memory cells comprises at least:
a lower data state; and
a higher data state higher than the lower data state; and
the identification circuit is further configured to identify at least one of:
a fastest subgroup of memory cells when the state change circuit alters the data state of at least some of the memory cells from the lower data state to the higher data state; and
a slowest subgroup of memory cells when the state change circuit alters the data state of at least some of the memory cells from the lower data state to the higher data state.
4. The apparatus of claim 1 , further comprising a counting circuit configured to count a total number of memory cells that satisfy a programming threshold and determine whether the total number of memory cells satisfies a numeric threshold, and wherein the identification circuit is configured to identify the subgroup of memory cells that satisfies the state change characteristic in response to the total number of memory cells that satisfy the programming threshold being greater than the numeric threshold.
5. The apparatus of claim 4 , wherein the numeric threshold comprises at least one of:
a pre-determined number; and
a percentage of the memory cells.
6. The apparatus of claim 1 , wherein the identification circuit is configured to identify the subgroup of memory cells during each programming procedure.
7. The apparatus of claim 1 , wherein the identification circuit is configured to identify the subgroup of memory cells according to a pre-determined schedule.
8. The apparatus of claim 1 , wherein the identified subgroup of memory cells comprises a tier group.
9. A non-volatile memory storage system comprising:
an array of memory cells organized into multiple subgroups;
a programming circuit configured to apply one or more programming pulses to the array of memory cells to program the memory cells to a target data state;
a counting circuit configured to count a first number of cells of a first subgroup that satisfy a threshold and count a second number of cells of a second subgroup that satisfy the threshold; and
an identification circuit configured to identify the first subgroup as a fastest memory cell subgroup and the second subgroup as a slowest memory cell subgroup in response to the first number of cells being greater than the second number of cells.
10. The non-volatile memory storage system of claim 9 , wherein the identification circuit is further configured to identify at least one intermediate programming speed memory cell subgroup.
11. The non-volatile memory storage system of claim 9 , wherein:
the target data state of the memory cells comprises at least one of:
a lower data state; and
a higher data state higher than the lower data state; and
the identification circuit is further configured to identify at least one of:
the fastest memory cell subgroup when the programming circuit programs the memory cells from the lower data state to the higher data state; and
the slowest memory cell subgroup when the programming circuit programs the memory cells from the lower data state to the higher data state.
12. The non-volatile memory storage system of claim 9 , wherein the identification circuit is configured to identify the fastest memory cell subgroup and the slowest memory cell subgroup during each programming procedure.
13. The non-volatile memory storage system of claim 9 , wherein the identification circuit is configured to identify the fastest memory cell subgroup and the slowest memory cell subgroup according to a pre-determined schedule.
14. The non-volatile memory storage system of claim 9 , wherein the fastest memory cell subgroup and the slowest memory cell subgroup comprise tiers.
15. A memory apparatus configured to:
apply one or more programming pulses to subgroups of memory cells in a programming operation;
count a total number of the memory cells that satisfy a programming threshold;
determine whether the total number is greater than a numeric threshold;
determine a number of memory cells within each subgroup that satisfy the programming threshold in response to determining that the total number is greater than the numeric threshold;
identify at least one of a fastest programming subgroup and a slowest programming subgroup based on the determined number of memory cells within each subgroup; and
utilize the identified subgroup for subsequent verification steps of the programming operation.
16. The memory apparatus of claim 15 , wherein:
applying the one or more programming pulses to subgroups of memory cells in the programming operation alters a data state of at least some of the memory cells, the data state comprising at least:
a lower data state; and
a higher data state higher than the lower data state; and
identifying the at least one of the fastest programming subgroup and the slowest programming subgroup further comprises at least one of:
identifying the fastest programming subgroup when the programming operation alters the data state of at least some of the memory cells from the lower data state to the higher data state; and
identifying the slowest programming subgroup when the programming operation alters the data state of at least some of the memory cells from the lower data state to the higher data state.
17. The memory apparatus of claim 15 , further comprising identifying an intermediate programming speed subgroup based on the determined number of memory cells within each subgroup.
18. The memory apparatus of claim 15 , wherein identifying the at least one of the fastest programming subgroup and the slowest programming subgroup is performed during each programming operation.
19. The memory apparatus of claim 15 , wherein identifying the at least one of the fastest programming subgroup and the slowest programming subgroup is performed according to a pre-determined schedule.
20. The memory apparatus of claim 15 , wherein the programming threshold comprises a programming verification level.