Backplane structure and process for microdriver and micro LED
Micro LED and microdriver chip integration schemes are described. In an embodiment a microdriver chip includes a plurality of trenches formed in a bottom surface of the microdriver chip, with each trench surrounding a conductive stud extending below a bottom surface of the microdriver chip body. Integration schemes are additionally described for providing electrical connection to conductive terminal contacts and micro LEDs bonded to a display substrate and adjacent to a microdriver chip.
1. A chip comprising:
a device layer;
a build-up layer below the device layer, the build-up layer including a plurality of landing pads;
a passivation layer below the build-up layer, the passivation layer including a bottom surface;
a plurality of trenches formed completely through the passivation layer to expose the plurality of landing pads;
a barrier layer spanning the bottom surface of the passivation layer, sidewalls of the plurality of trenches and the plurality of landing pads, wherein the barrier layer is thinner than the passivation layer and has a topography that is conformal to a topography of the bottom surface of the passivation layer, the sidewalls of the plurality of trenches and the plurality of landing pads;
a plurality of stud openings in the barrier layer within the plurality of trenches, and a corresponding plurality of conductive studs extending from the plurality of landing pads and through the plurality of stud openings in the barrier layer within the plurality of trenches;
wherein each conductive stud completely fills a corresponding stud opening in the barrier layer and is surrounded by sidewalls of the barrier layer within a corresponding trench such that a reservoir is formed between the conductive stud and the sidewalls of the barrier layer within the corresponding trench; and
each conductive stud includes a bottom surface that is below the bottom surface of the passivation layer.
2. The chip of claim 1 , wherein the barrier layer provides a non-wetting surface for solder reflow.
3. The chip of claim 2 , wherein the barrier layer is less than 2,000 Angstroms thick.
4. The chip of claim 3 , wherein the barrier layer comprises aluminum oxide (Al 2 O 3 ).
5. A display comprising:
a display substrate including an array of contact pads;
an array of light emitting diodes (LEDs) bonded to the display substrate;
an array of chips bonded to the display substrate;
wherein each chip is electrically connected to one or more LEDs to drive the one or more LEDs;
wherein each chip includes:
a device layer;
a build-up layer below the device layer, the build-up layer including a plurality of landing pads;
a passivation layer below the build-up layer, the passivation layer including a bottom surface;
a plurality of trenches formed completely through the passivation layer to expose the plurality of landing pads;
a barrier layer spanning the bottom surface of the passivation layer, sidewalls of the plurality of trenches and the plurality of landing pads, wherein the barrier layer is thinner than the passivation layer has a topography that is conformal to a topography of the bottom surface of the passivation layer, the sidewalls of the plurality of trenches and the plurality of landing pads;
a plurality of stud openings in the barrier layer within the plurality of trenches, and a corresponding plurality of conductive studs extending from the plurality of landing pads and through the plurality of stud openings in the barrier layer within the plurality of trenches;
wherein each conductive stud completely fills a corresponding stud opening in the barrier layer and is surrounded by sidewalls of the barrier layer within a corresponding trench such that a reservoir is formed between the conductive stud and the sidewalls of the barrier layer within the corresponding trench; and
each conductive stud includes a bottom surface that is below the bottom surface of the passivation layer;
wherein each conductive stud is bonded to a contact pad with a solder material that is reflowed into the reservoir of a corresponding trench.
6. The display of claim 5 , further comprising:
an array of conductive terminal lines on the display substrate;
a top contact layer on and in electrical connection with the array of LEDs, and on and in electrical connection with the array of conductive terminal lines.
7. The display of claim 5 , further comprising:
an array of conductive terminal posts on the display substrate;
a top contact layer on and in electrical connection with the array of LEDs, and on and in electrical connection with the array of conductive terminal posts.
8. The display of claim 5 , further comprising:
a patterned insulating layer covering edges of the array of contact pads;
wherein each chip is bonded to a plurality of contact pads directly over a corresponding portion of the patterned insulating layer.
9. A display comprising:
a display substrate;
a plurality of contact pads on the display substrate;
a chip bonded to the plurality of contact pads;
a bank structure laterally adjacent to the chip;
a trace line electrically connecting one of the plurality of contact pads to an LED contact pad on top of the bank structure, wherein the LED contact pad is raised above the plurality of contact pads on the display substrate;
an LED bonded to the LED contact pad.
10. The display of claim 9 , wherein the trace line runs along a sidewall of the bank structure.
11. The display of claim 9 , further comprising:
a passivation fill layer around sidewalls of the LED and the chip; and
a top contact layer spanning over the passivation fill layer, the LED, and the chip, wherein the top contact layer is on and in electrical contact with the LED and a conductive terminal contact.
12. The display of claim 11 , wherein the bank structure comprises a first bank level, and a second bank level on the first bank level, and the conductive terminal contact is on the second bank level.
13. The display of claim 12 , wherein the second bank level is integrally formed with the first bank level.
14. The display of claim 11 , further comprising:
an opening in the passivation fill layer over the conductive terminal contact;
wherein the conductive terminal contact is on the bank structure, and the top contact layer spans along sidewalls of the opening in the passivation fill layer.
15. The display of claim 11 , further comprising:
a second bank structure laterally adjacent to the bank structure;
an opening in the passivation fill layer over the conductive terminal contact;
wherein the conductive terminal contact is on the second bank structure, and the top contact layer spans along sidewalls of the opening in the passivation fill layer.
16. The display of claim 11 , further comprising:
a patterned insulating layer covering edges of the plurality of contact pads;
wherein the chip is bonded to the plurality of contact pads directly over a portion of the patterned insulating layer.
17. The display of claim 11 , wherein the passivation fill layer includes a top surface and a conformal bottom surface.
18. The display of claim 17 , wherein the conformal bottom surface is conformal to a topography of a conductive terminal contact on the bank structure, and the trace line electrically connecting one of the plurality of contact pads to the LED contact pad.
19. The display of claim 11 , wherein the chip comprises:
a device layer;
a passivation layer below the device layer, the passivation layer including a bottom surface;
a plurality of trenches in the passivation layer;
a plurality of conductive studs within the plurality of trenches;
a plurality of conductive studs within the plurality of trenches and extended below a bottom surface of the passivation layer;
wherein each conductive stud is bonded to a contact pad with a solder material that is reflowed into a corresponding trench.
20. The display of claim 9 , wherein a top surface of the LED is within at least 2 μm of a top surface of the adjacent chip, and the bank structure is formed of an electrically insulating material.