IP Library Granted Patent US 10,546,922
Granted Patent B2
US 10,546,922 · App. 15/890,320 · Granted Jan 28, 2020

Method for fabricating cap layer on an epitaxial layer

Inventors: Chih-Kai Hsu (Tainan, TW); Ssu-I Fu (Kaohsiung, TW); Yu-Hsiang Hung (Tainan, TW); Wei-Chi Cheng (Kaohsiung, TW); Jyh-Shyang Jenq (Pingtung County, TW); Tsung-Mu Yang (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/0653H01L21/28518H01L21/76805H01L21/76843H01L21/76855H01L21/76895H01L23/485H01L23/535H01L29/0847H01L29/41791H01L29/66795H01L29/785H01L29/7851
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Quick Facts
Patent No.
US 10,546,922
App. No.
15/890,320
Granted
Jan 28, 2020
Kind
B2
Abstract

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.

Claims (20)

1. A method for fabricating semiconductor device, comprising:

providing a substrate;

forming a gate structure on the substrate;

forming a recess in the substrate adjacent to two sides of the gate structure;

forming an epitaxial layer in the recess, wherein a top surface of the epitaxial layer is lower than a top surface of the substrate;

forming a cap layer on the epitaxial layer, wherein a top surface of the cap layer is higher than a top surface of the substrate, the top surface and a bottom surface of the cap layer comprise a first V-shape, and the cap layer and the epitaxial layer comprise same material; and

forming a silicide on the cap layer, wherein the silicide comprises a second V-shape, wherein a width of the second V-shape of the silicide is less than a width of the first V-shape of the cap layer.

2. The method of claim 1 , further comprising forming a buffer layer in the recess before forming the epitaxial layer.

3. The method of claim 2 , wherein the buffer layer comprises silicon phosphide (SiP).

4. The method of claim 1 , wherein the epitaxial layer and the cap layer comprises SiP.

5. The method of claim 4 , wherein a concentration of the phosphorus in the cap layer is lower than a concentration of the phosphorus in the epitaxial layer.

6. The method of claim 1 , wherein a top surface of the epitaxial layer comprises a V-shaped profile.

7. The method of claim 1 , wherein the cap layer comprises a triangular shape.

8. The method of claim 7 , further comprising:

forming a contact plug to contact the cap layer and transforming the triangular shape of the cap layer into the first V-shape.

9. The method of claim 8 , wherein a width of the contact plug is less than a width of the first V-shape of the cap layer and equal to a width of the second V-shape of the silicide.

10. The method of claim 8 , wherein a width of the contact plug is less than a width of the first V-shape of the cap layer and less than a width of the second V-shape of the silicide.

11. The method of claim 1 , wherein a thickness of the cap layer is between 10-100 Angstroms.

12. The method of claim 1 , wherein a topmost surface of the first V-shape of the cap layer is higher than a top surface of the substrate.

13. The method of claim 1 , wherein a topmost surface of the second V-shape of the silicide is higher than a top surface of the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2025
From: UNITED MICROELECTRONICS CORP.
To: STELLAR SEMICONDUCTOR JAPAN GK
Reel/Frame 071913/0125 →
Priority Claims (1)
CN 2016 1 0209916 · Apr 6, 2016 · national
Continuity (2)
Division 15144842 · May 3, 2016
Related Publication 20180166532A1 · Jun 14, 2018
Cited By (1)
US 12,356,677