IP Library › Granted Patent US 10,566,137
Granted Patent B2
US 10,566,137 · App. 15/856,590 · Granted Feb 18, 2020

Multilayer electronic component and board having the same

Inventors: Se Hun Park (Suwon-si, KR); Gu Won Ji (Suwon-si, KR); Heung Kil Park (Suwon-si, KR)
Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
H01G4/12H01G2/06H01G4/01H01G4/224H01G4/30H05K1/0271
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Quick Facts
Patent No.
US 10,566,137
App. No.
15/856,590
Granted
Feb 18, 2020
Kind
B2
Abstract

A multilayer electronic component includes: a capacitor body including an active region including first and second internal electrodes and upper and lower cover regions; first and second external electrodes including first and second connected portions connected to the first and second internal electrodes and first and second band portions, respectively; and first and second bump terminals having conductive layers and disposed on the first and second band portions, respectively, wherein BW/3≤G≤BW and T/5<ET<T/2, where BW is a width of each of the first and second band portions, T is a thickness of each of the first and second connected portions, G is a width of each of the first and second bump terminals, and ET is a thickness of each of the first and second bump terminals.

Claims (30)

1. A multilayer electronic component comprising:

a capacitor body having first and second surfaces opposing each other in a thickness direction and third and fourth surfaces connected to the first and second surfaces and opposing each other in a length direction, and including an active region including first and second internal electrodes disposed to be alternately exposed through the third and fourth surfaces, respectively, with respective dielectric layers interposed therebetween and upper and lower cover regions disposed on upper and lower surfaces of the active region, respectively;

first and second external electrodes including, respectively, first and second connected portions disposed on the third and fourth surfaces of the capacitor body, respectively, and connected to the first and second internal electrodes, respectively, and first and second band portions extending from the first and second connected portions to portions of the first surface; and

first and second bump terminals formed of insulators, having conductive layers formed on surfaces thereof, and disposed on the first and second band portions, respectively,

wherein BW/3≤G≤BW and ⅕<ET/T<½, where BW is a dimension of each of the first and second band portions in the length direction, T is a dimension in the thickness direction of each of the first and second external electrodes extending along the third and fourth surfaces, respectively, G is a dimension of each of the first and second bump terminals in the length direction, and ET is a dimension of each of the first and second bump terminals in the thickness direction.

2. The multilayer electronic component of claim 1 , wherein the lower cover region has a thickness greater than that of the upper cover region.

3. The multilayer electronic component of claim 2 , wherein the thickness of the lower cover region is less than two times of that of the upper cover region.

4. The multilayer electronic component of claim 1 , wherein the first external electrode extends to portions of the second surface and fifth and sixth surfaces of the capacitor body, and the second external electrode extends to portions of the second, fifth, and sixth surfaces of the capacitor body.

5. The multilayer electronic component of claim 1 , further comprising first and second insulating layers disposed on the first and second connected portions, respectively.

6. The multilayer electronic component of claim 1 , further comprising an encapsulating portion covering the capacitor body and the first and second external electrodes.

7. The multilayer electronic component of claim 1 , wherein the first and second bump terminals are disposed to be spaced apart from the first and second connected portions, respectively.

8. The multilayer electronic component of claim 7 , further comprising step portions on the first and second band portions between the first and second bump terminals and the first and second connected portions, respectively.

9. The multilayer electronic component of claim 1 , wherein W/2<EW<W, where W is a dimension of each of the first and second connected portions in a width direction and EW is a dimension of each of the first and second bump terminals in the width direction.

10. The multilayer electronic component of claim 1 , wherein the conductive layers are formed by plating.

11. The multilayer electronic component of claim 1 , wherein the first and second bump terminals are formed of insulation epoxy.

12. A board having a multilayer electronic component, comprising:

a circuit board having first and second electrode pads disposed thereon; and

the multilayer electronic component of claim 1 disposed on the circuit board so that the first and second bump terminals are connected to the first and second electrode pads, respectively.

13. The multilayer electronic component of claim 1 , wherein portions of the first and second external electrodes disposed on the third and fourth surfaces are free of the insulators of the first and second bump terminals.

14. The multilayer electronic component of claim 1 , wherein the insulators of the first and second bump terminals are disposed directly on the first and second band portions of the first and second external electrodes, respectively, over the entire extent BW of each of the first and second band portions in the length direction.

15. A multilayer electronic component comprising:

a capacitor body having first and second surfaces opposing each other in a thickness direction and third and fourth surfaces connected to the first and second surfaces and opposing each other in a length direction, and including an active region including first and second internal electrodes disposed to be alternately exposed through the third and fourth surfaces, respectively, with respective dielectric layers interposed therebetween and upper and lower cover regions disposed on upper and lower surfaces of the active region, respectively;

first and second external electrodes including, respectively, first and second connected portions disposed on the third and fourth surfaces of the capacitor body, respectively, and connected to the first and second internal electrodes, respectively, and first and second band portions extending from the first and second connected portions to portions of the first surface; and

first and second bump terminals disposed on the first and second band portions, respectively,

wherein the first and second bump terminals are spaced apart from the third and fourth surfaces of the capacitor body, respectively, and

wherein BW/3≤G≤BW and ⅕<ET/T<½, where BW is a dimension of each of the first and second band portions in the length direction, T is a dimension in the thickness direction of each of the first and second external electrodes extending along the third and fourth surfaces, respectively, G is a dimension of each of the first and second bump terminals in the length direction, and ET is a dimension of each of the first and second bump terminals in the thickness direction.

16. The multilayer electronic component of claim 15 , wherein the first and second bump terminals are formed of insulators and have conductive layers formed on surfaces thereof.

17. The multilayer electronic component of claim 15 , wherein W/2<EW<W, where W is a dimension of each of the first and second connected portions in a width direction and EW is a dimension of each of the first and second bump terminals in the width direction.

18. The multilayer electronic component of claim 15 , wherein portions of the first and second external electrodes disposed on the third and fourth surfaces are free of the first and second bump terminals.

19. The multilayer electronic component of claim 15 , wherein the first and second bump terminals are disposed directly on the first and second band portions of the first and second external electrodes, respectively, over the entire extent BW of each of the first and second band portions in the length direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2017
From: PARK, SE HUN; JI, GU WON; PARK, HEUNG KIL
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 044499/0973 →
Priority Claims (1)
KR 10-2017-0128505 · Oct 2, 2017 · national
Continuity (1)
Related Publication 20190103221A1 · Apr 4, 2019
Cited By (3)
US 12,469,644 US 12,597,564 US 12,640,308