Nanosheet transistors with thin inner spacers and tight pitch gate

1. A method for fabricating a semiconductor structure comprising:

forming a nanosheet stack structure on a semiconductor substrate, wherein the nanosheet stack structure comprises a multilayered nanosheet between adjacent nanosheet layers, and further wherein the multilayered nanosheet comprises one or more first layers of a first material and one or more second layers of a second material, wherein the first material has an etch selectivity different than the second material;

recessing the one or more first layers of the multilayered nanosheet;

forming a first inner spacer comprising a third material, wherein forming the first inner spacer comprises depositing the third material into an outer portion of the one or more recessed first layers of the multilayered nanosheet;

recessing the second layer of the multilayered nanosheet; and

forming a second inner spacer comprising a fourth material, wherein forming the second inner spacer comprises depositing the fourth material into an outer portion of the one or more recessed second layers of the first multilayered nanosheet.

2. The method of claim 1 , wherein the multilayered nanosheet comprises at least two layers.

3. The method of claim 1 , wherein the multilayered nanosheet comprises at least three layers.

4. The method of claim 1 , wherein the multilayered nanosheet is comprised of alternating layers of Si x Ge y .

5. The method of claim 1 , wherein the adjacent nanosheet layers are silicon, and the multilayered nanosheet is comprised of alternating layers of Si x Ge y .

6. The method of claim 5 , wherein the multilayered nanosheet is comprised of Si 60 Ge 40 /Si 80 Ge 20 /Si 60 Ge 40 layers.

7. The method of claim 1 , wherein the step of forming the first inner spacer further comprises:

depositing the third material on an exterior surface of the semiconductor substrate and the nanosheet stack structure including the outer portion of the one or more recessed first layers of the multilayered nanosheet; and

etching back the third material to expose the exterior surface of the semiconductor substrate and the adjacent nanosheet layers of the nanosheet stack structure.

8. The method of claim 7 , wherein the step of forming the second inner spacer further comprises:

depositing the fourth material on the exterior surface of the semiconductor substrate and the nanosheet stack structure including the outer portion of the one or more recessed second layers of the multilayered nanosheet; and

etching back the fourth material to expose the exterior surface of the semiconductor substrate and the adjacent nanosheet layers of the nanosheet stack structure.

9. The method of claim 1 , further comprising forming a cladding spacer and a dummy gate around the nanosheet stack structure prior to recessing steps.

10. The method of claim 9 , further comprising selectively removing the dummy gate.

11. The method of claim 10 , further comprising forming a replacement metal gate.

12. The method of claim 11 , further comprising forming a gate dielectric layer prior to forming the replacement metal gate.

13. The method of claim 12 , further comprising forming at least one interlayer dielectric and at least one source/drain region after the step of forming the second inner spacer.

14. The method of claim 1 , further comprising forming isolation layers in a surface region of a base adjacent to the nanosheet stack structure.

15. The method of claim 14 , wherein a first and second source/drain regions are disposed on the isolation layers and isolated from the base by the isolation layers.

16. The method of claim 1 , wherein a base comprises a semiconductor substrate.

17. The method of claim 16 , wherein the semiconductor substrate is comprised of silicon.