Semiconductor device and method for fabricating thereof
A semiconductor device includes a lower pattern extending in a first direction and sheet patterns spaced apart therefrom in a second direction, a gate structure on the lower pattern and including a gate insulating layer, a gate spacer, and a gate electrode, a source/drain pattern on the lower pattern and in contact with each of the sheet patterns and the gate insulating layer, and a first etch blocking pattern between the gate spacer and the source/drain pattern. The gate spacer includes an inner sidewall extending in the third direction, and a connection sidewall extending from the inner sidewall in the first direction. The source/drain pattern includes a semiconductor filling layer on a semiconductor liner layer that is in contact with the sheet pattern and includes a facet surface extending from the connection sidewall. The first etch blocking pattern is in contact with the facet surface and the connection sidewall.
1 . A semiconductor device comprising:
an active pattern comprising a lower pattern extending in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction;
a gate structure on the lower pattern and comprising a gate insulating layer, a gate electrode, and a gate spacer, the gate electrode extending in a third direction perpendicular to the first direction;
a source/drain pattern on the lower pattern and in contact with the sheet patterns and the gate insulating layer; and
a first etch blocking pattern between the gate spacer and the source/drain pattern,
wherein the gate spacer comprises an inner sidewall facing the gate electrode and extending in the third direction, and a connection sidewall extending from the inner sidewall of the gate spacer in the first direction,
the source/drain pattern comprises a semiconductor liner layer and a semiconductor filling layer on the semiconductor liner layer,
the semiconductor liner layer is in contact with the sheet patterns, and comprises a facet surface extending from the connection sidewall of the gate spacer, and
the first etch blocking pattern is in contact with the facet surface of the semiconductor liner layer and the connection sidewall of the gate spacer.
2 . The semiconductor device of claim 1 , wherein a width of the first etch blocking pattern in the third direction increases with distance in the first direction away from the gate electrode.
3 . The semiconductor device of claim 1 , wherein the first etch blocking pattern comprises an insulating material.
4 . The semiconductor device of claim 1 , wherein the first etch blocking pattern comprises a blocking liner extending along the facet surface of the semiconductor liner layer and the connection sidewall of the gate spacer, and a blocking filling layer on the blocking liner.
5 . The semiconductor device of claim 1 , wherein the gate structure comprises an inner gate structure between the lower pattern and the sheet patterns and between the sheet patterns adjacent to each other, the inner gate structure comprising the gate electrode and the gate insulating layer, and
the first etch blocking pattern is between the inner gate structure and the semiconductor filling layer.
6 . The semiconductor device of claim 1 , wherein the first etch blocking pattern comprises a first surface facing the facet surface of the semiconductor liner layer, a second surface facing the connection sidewall of the gate spacer, and a connection surface extending from the first surface to the second surface, and
an entirety of the connection surface of the first etch blocking pattern is in contact with the semiconductor filling layer.
7 . The semiconductor device of claim 1 , wherein the source/drain pattern comprises an air gap between the first etch blocking pattern and the semiconductor filling layer.
8 . The semiconductor device of claim 1 , further comprising:
a second etch blocking pattern in the source/drain pattern,
wherein the second etch blocking pattern is between the semiconductor liner layer and the semiconductor filling layer, and
a width of the second etch blocking pattern in the third direction increases with distance in the first direction away from the gate electrode.
9 . The semiconductor device of claim 8 , wherein the source/drain pattern comprises an air gap between the second etch blocking pattern and the semiconductor filling layer.
10 . The semiconductor device of claim 8 , wherein the second etch blocking pattern comprises first and second surfaces in contact with the semiconductor liner layer and a connection surface extending from the first surface to the second surface, and
an entirety of the connection surface of the second etch blocking pattern is in contact with the semiconductor filling layer.
11 . The semiconductor device of claim 1 , wherein each of the semiconductor liner layer and the semiconductor filling layer comprises silicon-germanium.
12 . A semiconductor device comprising:
an active pattern comprising a lower pattern elongated in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction;
a gate structure on the lower pattern and comprising a gate insulating layer, a gate electrode, and a gate spacer, the gate electrode elongated in a third direction perpendicular to the first direction; and
a source/drain pattern on the lower pattern and in contact with the sheet patterns and the gate insulating layer,
wherein the source/drain pattern comprises a semiconductor liner layer and a semiconductor filling layer on the semiconductor liner layer and in contact with the semiconductor liner layer,
the semiconductor liner layer is in contact with the sheet patterns, and comprises a facet surface extending from the gate spacer, and
in plan view at a level of one of the sheet patterns, a first width comprising a maximum width of the semiconductor liner layer in the third direction is greater than a second width, in the third direction, of an interface between the semiconductor liner layer and the semiconductor filling layer.
13 . The semiconductor device of claim 12 , wherein in plan view, the semiconductor filling layer is in contact with a portion of the facet surface of the semiconductor liner layer.
14 . The semiconductor device of claim 12 , further comprising:
an etch blocking pattern between the gate spacer and the source/drain pattern,
wherein the gate spacer comprises an inner sidewall facing the gate electrode and extending in the third direction and a connection sidewall extending from the inner sidewall of the gate spacer in the first direction, and
the etch blocking pattern is in contact with the facet surface of the semiconductor liner layer and the connection sidewall of the gate spacer.
15 . The semiconductor device of claim 14 , wherein in plan view, the etch blocking pattern further comprises a third surface extending between the facet surface of the semiconductor liner layer and the connection sidewall of the gate spacer, and the third surface is concave.
16 . A semiconductor device comprising:
a first active pattern comprising a first lower pattern extending in a first direction and a plurality of first sheet patterns spaced apart from the first lower pattern in a second direction;
a first gate structure on the first lower pattern and comprising a first gate insulating layer, a first gate electrode, and a first gate spacer, the first gate electrode extending in a third direction perpendicular to the first direction;
a second active pattern comprising a second lower pattern extending in the first direction and a plurality of second sheet patterns spaced apart from the second lower pattern in the second direction, a width of an upper surface of the second lower pattern in the third direction being smaller than a width of an upper surface of the first lower pattern in the third direction;
a second gate structure on the second lower pattern and comprising a second gate insulating layer, a second gate electrode, and a second gate spacer, the second gate electrode extending in the third direction;
a first source/drain pattern on the first lower pattern and in contact with the first sheet patterns and the first gate insulating layer;
a second source/drain pattern on the second lower pattern and in contact with the second sheet patterns and the second gate insulating layer; and
a first etch blocking pattern between the first gate spacer and the first source/drain pattern,
wherein the first gate spacer comprises an inner sidewall facing the first gate electrode and extending in the third direction and a connection sidewall extending from the inner sidewall of the first gate spacer in the first direction,
the first source/drain pattern comprises a semiconductor liner layer and a semiconductor filling layer on the semiconductor liner layer,
the semiconductor liner layer is in contact with the first sheet patterns, and comprises a facet surface extending from the connection sidewall of the first gate spacer, and
the first etch blocking pattern is in contact with the facet surface of the semiconductor liner layer and the connection sidewall of the first gate spacer.
17 . The semiconductor device of claim 16 , wherein the second gate spacer and the second source/drain pattern are free of an etch blocking pattern therebetween.
18 . The semiconductor device of claim 16 , further comprising:
a second etch blocking pattern between the second gate spacer and the second source/drain pattern,
wherein a dimension of the first etch blocking pattern in the first direction is greater than a dimension of the second etch blocking pattern in the first direction.
19 . The semiconductor device of claim 16 , wherein the first etch blocking pattern comprises a blocking liner extending along the facet surface of the semiconductor liner layer and the connection sidewall of the first gate spacer, and a blocking filling layer on the blocking liner.
20 . The semiconductor device of claim 16 , further comprising:
a second etch blocking pattern in the first source/drain pattern,
wherein the second etch blocking pattern is between the semiconductor liner layer and the semiconductor filling layer,
a width of the second etch blocking pattern in the third direction increases with distance from the first gate electrode, and
the second source/drain pattern is free of an etch blocking pattern therein.