Test access port, test clock inverter, and shadow access port
The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.
1. An integrated circuit comprising:
(A) a TCK terminal, a TMS terminal, a TDI terminal, and a TDO terminal;
(B) a test access port circuit including:
(i) a test data register having an input coupled to the TDI terminal, a test TDO enable input, and an output selectively coupled to the TDO terminal;
(ii) a test instruction register having an input coupled to the TDI terminal, a test TDO enable input, and an output selectively coupled to the TDO terminal; and
(iii) a test state machine having an input that is coupled to the TCK terminal, an input that is coupled to the TMS terminal, and a test TDO enable output that is coupled to the test TDO enable inputs of the test data register and the test instruction register, the test state machine changing states upon a rising edge of a clock signal on the TCK terminal;
(C) an inverter having an input coupled to the TCK terminal and an output; and
(D) a shadow access port circuit having:
(i) a shadow data register having an input coupled to the TDI terminal, a shadow TDO enable input, and an output selectively coupled to the TDO terminal;
(ii) a shadow instruction register having an input coupled to the TDI terminal, a shadow TDO enable input, and an output selectively coupled to the TDO terminal; and
(iii) a shadow state machine having an input that is coupled to the TCK terminal, an input that is coupled to the TMS terminal, and a shadow TDO enable output that is coupled to the shadow TDO enable inputs of the shadow data register and the shadow instruction register, the shadow state machine changing states upon a falling edge of a clock signal on the TCK terminal.
2. The integrated circuit of claim 1 in which the test state machine steps through the states of SELECT-DR, CAPTURE-DR, SHIFT-DR, EXIT1-DR, PAUSE-DR, EXIT2-DR, and UPDATE-DR.
3. The integrated circuit of claim 1 in which the shadow state machine steps through the states of SELECT-DR, CAPTURE-DR, SHIFT-DR, and UPDATE-DR without shifting through states of EXIT1-DR, PAUSE-DR, or EXIT2-DR.
4. The integrated circuit of claim 1 in which the test state machine has a RESET state and an IDLE state and the shadow state machine has a RESET state and an IDLE state.
5. The integrated circuit of claim 1 in which the test TDO enable output is separate from the shadow TDO enable output.
6. The integrated circuit of claim 1 in which the test data register is separate from the shadow data register.
7. The integrated circuit of claim 1 in which the test instruction register is separate from the shadow instruction register.
8. The integrated circuit of claim 1 in which the test state machine is separate from the shadow state machine.
9. The integrated circuit of claim 1 including test multiplexer circuitry having an input coupled to the output of the test data register, an input coupled to the output of the test instruction register, an input coupled to the test TDO enable output, and an output coupled to the TDO terminal.
10. The integrated circuit of claim 1 including shadow multiplexer circuitry having an input coupled to the output of the shadow data register, an input coupled to the output of the shadow instruction register, an input coupled to the shadow TDO enable output, and an output coupled to the TDO terminal.
11. The integrated circuit of claim 1 including:
(A) test multiplexer circuitry having an input coupled to the output of the test data register, an input coupled to the output of the test instruction register, an input coupled to the test TDO enable output, and an output coupled to the TDO terminal;
(B) shadow multiplexer circuitry having an input coupled to the output of the shadow data register, an input coupled to the output of the shadow instruction register, an input coupled to the shadow TDO enable output, and an output coupled to the TDO terminal; and
(C) the test multiplexer circuitry being separate from the shadow multiplexer circuitry.