Static random access memory cell employing n-doped PFET gate electrodes and methods of manufacturing the same

1. A static random access memory (SRAM), comprising:

a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground; and

a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground,

wherein:

each of the first p-type pull-up transistor, the first n-type pull-down transistor, the second p-type pull-up transistor, and the second n-type pull-down transistor comprises a respective n-doped gate electrode portion;

the first p-type pull-up transistor comprises a first-thickness gate dielectric having a first thickness;

the first n-type pull-down transistor comprises a second-thickness gate dielectric having a second thickness that is less than the first thickness; and

each n-doped gate electrode portion of the first p-type pull-up transistor, the first n-type pull-down transistor, the second p-type pull-up transistor, and the second n-type pull-down transistor comprises n-doped polysilicon which has a same material composition.

2. The SRAM of claim 1 , wherein the SRAM cell further comprises at least one pass gate transistor including an active region that is electrically shorted to an active region of one of the first and second series connections, wherein the at least one pass gate transistor comprises an n-doped gate electrode portion.

3. The SRAM of claim 2 , wherein the n-doped gate electrode portion of the at least one pass gate transistor has a same material composition as the n-doped gate electrode portions of the first p-type pull-up transistor, the first n-type pull-down transistor, the second p-type pull-up transistor, and the second n-type pull-down transistor.

4. A static random access memory (SRAM), comprising:

a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground; and

a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground,

wherein:

each of the first p-type pull-up transistor, the first n-type pull-down transistor, the second p-type pull-up transistor, and the second n-type pull-down transistor comprises a respective n-doped gate electrode portion;

the first p-type pull-up transistor comprises a first-thickness gate dielectric having a first thickness;

the first n-type pull-down transistor comprises a second-thickness gate dielectric having a second thickness that is less than the first thickness; and

an n-doped gate electrode portion of the first p-type pull-up transistor and an n-doped gate electrode portion of the first n-type pull-down transistor are portions of a first n-doped gate electrode.

5. The SRAM of claim 4 , wherein an n-doped gate electrode portion of the second p-type pull-up transistor and an n-doped gate electrode portion of the second n-type pull-down transistor are portions of a second n-doped gate electrode.

6. The SRAM of claim 4 , wherein:

the n-doped gate electrode portion of the first p-type pull-up transistor has a first uniform width;

the n-doped gate electrode portion of the first n-type pull-down transistor has a second uniform width that is less than the first uniform width; and

the first n-doped gate electrode has a connection region having a tapered width that changes from the first uniform width to the second uniform width.

7. The SRAM of claim 6 , further comprising a shallow trench isolation structure that laterally surrounds a first active area in which the first p-type pull-up transistor is located and a second active area in which the first n-type pull-down transistor is located, wherein the connection region of the first n-doped gate electrode overlies a portion of the shallow trench isolation structure located between the first active area and the second active area.

8. A static random access memory (SRAM), comprising:

a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground; and

a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground,

wherein:

each of the first p-type pull-up transistor, the first n-type pull-down transistor, the second p-type pull-up transistor, and the second n-type pull-down transistor comprises a respective n-doped gate electrode portion;

the first p-type pull-up transistor comprises a first-thickness gate dielectric having a first thickness;

the first n-type pull-down transistor comprises a second-thickness gate dielectric having a second thickness that is less than the first thickness; and

an n-doped gate electrode portion of the first p-type pull-up transistor and an n-doped gate electrode portion of the first n-type pull-down transistor are two discrete n-doped gate electrode portions that are not in direct contact with each other.

9. A static random access memory (SRAM), comprising:

a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground; and

a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground,

wherein:

each of the first p-type pull-up transistor, the first n-type pull-down transistor, the second p-type pull-up transistor, and the second n-type pull-down transistor comprises a respective n-doped gate electrode portion;

the first p-type pull-up transistor comprises a first-thickness gate dielectric having a first thickness;

the first n-type pull-down transistor comprises a second-thickness gate dielectric having a second thickness that is less than the first thickness;

the second p-type pull-up transistor comprises the first-thickness gate dielectric having a first thickness; and

the second n-type pull-down transistor comprises the second-thickness gate dielectric having a second thickness that is less than the first thickness.

10. The SRAM of claim 9 , wherein the SRAM is part of a driver circuit for a three-dimensional NAND memory device.

11. A method of forming a static random access memory (SRAM), comprising:

forming a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground over a semiconductor substrate, and

forming a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground over the semiconductor substrate,

wherein:

the first p-type pull-up transistor and the second p-type pull-up transistor comprise n-doped gate electrode portions;

the first and second p-type pull-up transistors are formed on first-thickness gate dielectrics having a first thickness;

the first and second n-type pull-down transistors are formed on second-thickness gate dielectrics having a second thickness that is less than the first thickness; and

each of the first p-type pull-up transistor, the first n-type pull-down transistor, the second p-type pull-up transistor, and the second n-type pull-down transistor is provided by forming a respective patterned n-doped gate electrode portion.

12. The method of claim 11 , wherein each patterned n-doped gate electrode portion of the first p-type pull-up transistor, the first n-type pull-down transistor, the second p-type pull-up transistor, and the second n-type pull-down transistor is formed by patterning an n-doped semiconductor material layer without any lateral compositional gradient in a same patterning step.

13. The method of claim 12 , wherein the SRAM cell further comprises at least one pass gate transistor including an active region that is electrically shorted to an active region of one of the first and second series connections, wherein a patterned n-doped gate electrode portion of the at least one pass gate transistor is formed by patterning the n-doped semiconductor material layer.

14. The method of claim 11 , wherein an n-doped gate electrode portion of the first p-type pull-up transistor and an n-doped gate electrode portion of the first n-type pull-down transistor are formed as portions of a first n-doped gate electrode.

15. The method of claim 14 , wherein an n-doped gate electrode portion of the second p-type pull-up transistor and an n-doped gate electrode portion of the second n-type pull-down transistor are portions of a second n-doped gate electrode.

16. The method of claim 15 , wherein:

the n-doped gate electrode portion of the first p-type pull-up transistor has a first uniform width;

the n-doped gate electrode portion of the first n-type pull-down transistor has a second uniform width that is less than the first uniform width; and

the first n-doped gate electrode has a connection region having a tapered width that changes from the first uniform width to the second uniform width.

17. The method of claim 11 , further comprising:

forming a first-thickness gate dielectric layer on a top surface of the semiconductor substrate;

patterning the first-thickness gate dielectric layer to form the first-thickness gate dielectrics;

forming a second-thickness gate dielectric layer on the top surface of the semiconductor substrate after formation of the first-thickness gate dielectrics; and

patterning the second-thickness gate dielectric layer to form the second-thickness gate dielectrics.