Metal-insulator-metal structure and methods of fabrication thereof

1. A metal-insulator-metal (MIM) capacitor structure, comprising:

a semiconductor substrate having a top surface;

a bottom conductive layer lying above the top surface of the semiconductor substrate, wherein the bottom conductive layer has a slanted sidewall with respect to the top surface of the semiconductor substrate;

a top conductive layer above the bottom conductive layer, wherein the top conductive layer has a vertical sidewall with respect to the top surface of the semiconductor substrate;

an insulating layer interposed between the bottom conductive layer and the top conductive layer, wherein the insulating layer covers the slanted sidewall of the bottom conductive layer; and

a middle conductive layer interposed between the bottom conductive layer and the top conductive layer, wherein the middle conductive layer is embedded in the insulating layer.

2. The MIM capacitor structure of claim 1 , wherein the slanted sidewall of the bottom conductive layer forms an angle between about 60 degrees and about 80 degrees with respect to the top surface of the semiconductor substrate.

3. The MIM capacitor structure of claim 1 , wherein the insulating layer is a high-k dielectric layer.

4. The MIM capacitor structure of claim 1 , wherein the middle conductive layer also has a slanted sidewall with respect to the top surface of the semiconductor substrate.

5. The MIM capacitor structure of claim 4 , wherein the slanted sidewall of the middle conductive layer forms an angle between about 60 degrees and about 80 degrees with respect to the top surface of the semiconductor substrate.

6. The MIM capacitor structure of claim 1 , wherein the insulating layer has a first sub layer and a second sub layer above the first sub layer, and wherein the first and second sub layers include different material compositions.

7. The MIM capacitor structure of claim 1 , further comprising:

a conductive feature having a sidewall, the sidewall having a top portion, a middle portion, and a bottom portion, the middle portion of the sidewall being in physical contact with the insulating layer and the bottom conductive layer, wherein the middle portion of the sidewall is tapered with respect to the top portion of the sidewall.

8. The MIM capacitor structure of claim 7 , where in the top portion and the bottom portion of the sidewall are substantially parallel.

9. The MIM capacitor structure of claim 7 , wherein the middle portion of the sidewall forms an angle between about 30 degrees and about 70 degrees with respect to the top surface of the semiconductor substrate.

10. The MIM capacitor structure of claim 7 , wherein extension lines along the middle portion of the sidewall intersect at a vertex, the vertex being above a bottom surface of the conductive feature.

11. A semiconductor device, comprising:

a bottom electrode disposed over a top surface of a semiconductor substrate;

a dielectric layer disposed over the bottom electrode;

a top electrode disposed over the dielectric layer; and

a via feature having a sidewall, a middle portion of the sidewall directly interfacing with the bottom electrode and the dielectric layer, the middle portion of the sidewall being tapered with respect to a top portion of the sidewall, wherein the top portion of the sidewall forms a first angle with respect to the top surface of the semiconductor substrate, the middle portion of the sidewall forms a second angle with respect to the top surface of the semiconductor substrate, and the second angle is smaller than the first angle.

12. The semiconductor device of claim 11 , wherein the second angle is between about 30 degrees and about 70 degrees.

13. The semiconductor device of claim 11 , further comprising:

a middle electrode interposing the bottom electrode and the top electrode, wherein the middle portion of the sidewall also directly interfaces with the top electrode, and wherein the middle electrode is electrically isolated from the via feature.

14. The semiconductor device of claim 11 , wherein the bottom electrode has a tapered sidewall tilting from a vertical direction of a top surface of the semiconductor substrate, and wherein the dielectric layer covers the tapered sidewall.

15. The semiconductor device of claim 14 , wherein the top electrode has a vertical sidewall with respect to the top surface of the semiconductor substrate.

16. A semiconductor device, comprising:

a bottom conductive layer over a semiconductor substrate, wherein a terminal of the bottom conductive layer has a first sidewall;

a middle conductive layer over the bottom conductive layer;

a top conductive layer over the middle conductive layer, wherein a terminal of the top conductive layer has a second sidewall, wherein the first sidewall is tilted with respect to the second sidewall;

a first conductive feature electrically coupled to the bottom and top conductive layers; and

a second conductive feature electrically coupled to the middle conductive layer.

17. The semiconductor device of claim 16 , wherein a terminal of the middle conductive layer has a third sidewall, where the third sidewall is tilted with respect to the second sidewall.

18. The semiconductor device of claim 16 , wherein a sidewall of the first conductive feature has a top portion, a middle portion, and a bottom portion, and wherein the middle portion of the sidewall is tilted with respect to both the top and bottom portions of the sidewall.

19. The semiconductor device of claim 16 , further comprising an insulating layer sandwiched by the bottom and top conductive layers, wherein the insulating layer has two sub layers of different material compositions.