Device with capping layer for improved residue defect and method of production thereof

1. A device comprising:

a magnetic random access memory (MRAM) cell in a first region and a logic area in a second region of a substrate, wherein the MRAM cell comprises a magnetic tunnel junction (MTJ) pillar between a top electrode and a bottom electrode;

an MTJ film over a portion of the bottom electrode;

a capping layer over a portion of the top electrode; and

a silicon nitride (SiN) liner on upper and side surfaces of the bottom electrode and on upper and side surfaces of the MTJ film.

2. The device according to claim 1 , further comprising:

a first low-k dielectric layer over the first region and the second region of the substrate;

an interconnect layer in the first low-k dielectric layer;

an Nblok layer over the interconnect layer and the first low-k dielectric layer; and

a second low-k dielectric layer over the Nblok layer.

3. The device according to claim 2 , further comprising:

the bottom electrode through the second low-k dielectric layer and the Nblok layer in the first region contacting the interconnect layer; and

the MTJ pillar over a portion of the MTJ film.

4. The device according to claim 3 , further comprising:

the SiN liner on sidewalls of the MTJ pillar and over the MTJ film and the second low-k dielectric layer; and

a third low-k dielectric layer over the SiN liner and the MTJ pillar.

5. The device according to claim 4 , further comprising:

the top electrode through the third low-k dielectric layer in the first region contacting the MTJ pillar, upper surface of the top electrode substantially coplanar to upper surface of the third low-k dielectric layer.

6. The device according to claim 4 , further comprising:

a fourth low-k dielectric layer over the third low-k dielectric layer and the capping layer in the first region, and over a portion of the third low-k dielectric layer in the second region, a trench to the top electrode in the first region and a T-shaped trench to the interconnect layer in the second region formed, respectively.

7. The device according to claim 2 , wherein the top electrode and the bottom electrode comprise tantalum nitride (TaN).

8. The device according to claim 1 , wherein the capping layer comprises silicon nitride (SiN).

9. The device according to claim 1 , wherein the capping layer is formed to a thickness of 30 nanometer (nm) to 50 nm.

10. A method comprising:

forming a magnetic random access memory (MRAM) cell in a first region and a logic area in a second region of a substrate, wherein the MRAM cell comprises a magnetic tunnel junction (MTJ) pillar between a top electrode and a bottom electrode;

forming an MTJ film over a portion of the bottom electrode;

forming a capping layer over a portion of the top electrode; and

forming a silicon nitride (SiN) liner on upper and side surfaces of the bottom electrode and on upper and side surfaces of the MTJ film.

11. The method according to claim 10 , further comprising:

forming a first low-k dielectric layer over the first region and the second region of the substrate;

forming an interconnect layer in the first low-k dielectric layer;

forming an Nblok layer over the interconnect layer and the first low-k dielectric layer; and

forming a second low-k dielectric layer over the Nblok layer.

12. The method according to claim 11 , further comprising:

forming the bottom electrode through the second low-k dielectric layer and the Nblok layer in the first region contacting the interconnect layer; and

forming an MTJ pillar over a portion of the MTJ film.

13. The method according to claim 12 , further comprising:

forming the SiN liner on sidewalls of the MTJ pillar and over the MTJ film and the second low-k dielectric layer;

forming a third low-k dielectric layer over the SiN liner and the MTJ pillar; and

forming the top electrode through the third low-k dielectric layer in the first region contacting the MTJ pillar.

14. The method according to claim 13 , comprising forming the capping layer by a method including:

conformally forming a silicon nitride (SiN) layer over the third low-k dielectric layer and the top electrode;

forming a photoresist over a portion of the SiN layer in the first region;

removing exposed SiN layer in the first region and the second region;

removing the photoresist;

forming a fourth low-k dielectric layer over the SiN layer and the third low-k dielectric layer;

removing a portion of the fourth low-k dielectric layer, the third low-k dielectric layer, the SiN liner, the second low-k dielectric layer and the Nblok layer in the second region exposing upper surface of the interconnect layer; and

removing a portion of the fourth low-k dielectric layer and the capping layer in the first region exposing upper surface of the top electrode.

15. The method according to claim 13 , comprising forming the top electrode by a method including:

removing a portion of the third low-k dielectric layer exposing upper surface of the MTJ pillar, forming a trench;

filling the trench with conducting material contacting the MTJ pillar, wherein the conducting materials comprises tantalum nitride (TaN); and

planarizing by chemical mechanical planarization (CMP), upper surface of the top electrode substantially coplanar to upper surface of the third low-k dielectric layer.

16. The method according to claim 12 , comprising forming the bottom electrode by a method including:

removing a portion of the second low-k dielectric layer and the Nblok layer, forming a trench; and

filling the trench with conducting materials contacting the interconnect layer, wherein the conducting materials comprises tantalum nitride (TaN).

17. A device comprising:

a magnetic random access memory (MRAM) cell in a first region and a logic area in a second region of a substrate, wherein the MRAM cell comprises a magnetic tunnel junction (MTJ) pillar between a top electrode and a bottom electrode;

an MTJ film over a portion of the bottom electrode;

a capping layer comprising silicon nitride (SiN) and formed to a thickness of 30 nanometer (nm) to 50 nm over a portion of the top electrode; and

a silicon nitride (SiN) liner on upper and side surfaces of the bottom electrode and on upper and side surfaces of the MTJ film.

18. The device according to claim 17 , further comprising:

an interconnect layer in a first low-k dielectric layer formed over the first region and the second region of the substrate;

an Nblok layer over the interconnect layer and the first low-k dielectric layer;

a second low-k dielectric layer over the Nblok layer;

the bottom electrode through the second low-k dielectric layer and the Nblok layer in the first region contacting the interconnect layer; and

the MTJ pillar over a portion of the MTJ film.

19. The device according to claim 18 , further comprising:

the SiN liner on sidewalls of the MTJ pillar and over the MTJ film and the second low-k dielectric layer;

a third low-k dielectric layer over the SiN liner and the MTJ pillar;

the top electrode through the third low-k dielectric layer in the first region contacting the MTJ pillar; and

a fourth low-k dielectric layer over the third low-k dielectric layer and the capping layer in the first region, and over a portion of the third low-k dielectric layer in the second region, a trench to the top electrode and a t-shaped trench to the interconnect layer formed, respectively.