Silicon nitride liner for promotion of mold adhesion in integrated circuits
An example an IC package including a liner for promotion of mold adhesion includes a conductive structure on a support surface; a mold material at least partially encasing the conductive structure; and a liner on a surface of the conductive structure between the surface of the conductive structure and the mold material, wherein the liner comprises a material including silicon and nitrogen.
1 . An integrated circuit (IC) package, comprising:
a conductive structure over a surface;
an IC die proximate the conductive structure and coupled to the surface, wherein the IC die has a first face facing the surface, a second face opposite the first face, and a side extending between the first face and the second face;
an insulator material at least partially encasing the conductive structure;
a first liner on a surface of the conductive structure, wherein the first liner is between the surface of the conductive structure and the insulator material, and wherein the first liner includes silicon and nitrogen; and,
a second liner on the side of the IC die, wherein the second liner is between the side of the IC die and the insulator material.
2 . The IC package of claim 1 , wherein the conductive structure comprises a pillar.
3 . The IC package of claim 1 , wherein:
the liner is a first liner,
the IC package further includes a second liner on at least a portion of the surface, and
the second liner includes silicon and nitrogen.
4 . The IC package of claim 1 , wherein the surface is between the conductive structure and a package substrate.
5 . A microelectronic assembly, comprising:
a conductive structure comprising a conductive pillar;
an IC die proximate the conductive structure, the IC die comprising first and second faces opposite one another, and further comprising sides extending between the first and second faces;
an insulator material encasing at least a portion of the IC die and the conductive structure;
a first liner on a surface of the conductive structure, wherein the first liner is between the surface of the conductive structure and the insulator material; and
a second liner on the sides of the IC die, wherein the second liner is between the sides of the IC die and the insulator material,
wherein the first and second liners include silicon and nitrogen.
6 . The microelectronic assembly of claim 5 , wherein the IC die is a first IC die, and the microelectronic assembly further includes a second IC die coupled to at least one of the first IC die and the conductive structure.
7 . The microelectronic assembly of claim 6 , the microelectronic assembly further includes a package substrate, and wherein at least a portion of at least one of the first IC die and the conductive structure is between the package substrate and the second IC die.
8 . The microelectronic assembly of claim 5 , wherein the IC die is over a surface, and the microelectronic assembly further includes:
the insulator material on at least a portion of the first face of the IC die facing the surface, and
a third liner between at least a portion of the insulator material on the portion of the first face of the IC die and a portion of the surface.
9 . The microelectronic assembly of claim 5 , wherein at least one of the first liner and the second liner includes silicon and nitrogen in a ratio of approximately 3 to 4.
10 . A process of making a microelectronic assembly, the process comprising:
providing a conductive structure comprising a pillar that includes copper;
providing an IC die proximate the conductive structure, the IC die comprising first and second faces opposite one another, and further comprising sides extending between the first and second faces;
providing an insulator material encasing at least a portion of the IC die and the conductive structure;
providing a first liner on a surface of the conductive structure, wherein the first liner is between the surface of the conductive structure and the insulator material; and
providing a second liner on the sides of the IC die, wherein the second liner is between the sides of the IC die and the insulator material;
wherein the first and second liners include silicon and nitrogen.
11 . The process of claim 10 , wherein the IC die is a first IC die, and the process further includes providing a second IC die coupled to at least one of the first IC die and the conductive structure.
12 . The IC package of claim 1 , wherein the second liner includes silicon and nitrogen.
13 . The IC package of claim 1 , wherein the conductive structure includes copper.
14 . The IC package of claim 1 , wherein the IC die is a first IC die, and the IC package further includes a second IC die coupled to at least one of the first IC die and the conductive structure.
15 . The microelectronic assembly of claim 5 , wherein the conductive pillar includes copper.
16 . The microelectronic assembly of claim 5 , further comprising a package substrate.
17 . An integrated circuit (IC) package, comprising:
a conductive structure over a surface;
an IC die proximate the conductive structure and coupled to the surface, wherein the IC die has a first face facing the surface, a second face opposite the first face, and a side extending between the first face and the second face;
an insulator material at least partially encasing the conductive structure, wherein a portion of the insulator material is on at least a portion of the first face of the IC die;
a first liner on a surface of the conductive structure, wherein the first liner is between the surface of the conductive structure and the insulator material, and wherein the first liner includes silicon and nitrogen; and
a second liner on at least a portion of the surface, wherein the second liner is between the insulator material on the portion of the first face of the IC die and the portion of the surface.
18 . The IC package of claim 17 , wherein the second liner includes silicon and nitrogen.
19 . The IC package of claim 17 , wherein the surface is between the conductive structure and a package substrate.
20 . The IC package of claim 17 , wherein the IC die is a first IC die, and the IC package further includes a second IC die coupled to at least one of the first IC die and the conductive structure.