IP Library Granted Patent US 10,790,467
Granted Patent B2
US 10,790,467 · App. 16/836,005 · Granted Sep 29, 2020

Display device and method of manufacturing the same

Inventors: Jaybum Kim (Seoul, KR); Eoksu Kim (Seoul, KR); Kyoungseok Son (Seoul, KR); Junhyung Lim (Seoul, KR); Jihun Lim (Hwaseong-si, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
H01L51/5203G09G3/32G09G3/3233H01L27/1108H01L27/3262H01L51/0096G09G2300/0426G09G2300/0814G09G2300/0842G09G2300/0861G09G2300/0866G09G2310/0245G09G2310/0262H01L27/3265H01L51/0023H01L51/5296H01L2227/323
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Quick Facts
Patent No.
US 10,790,467
App. No.
16/836,005
Granted
Sep 29, 2020
Kind
B2
Abstract

A display device includes a base substrate, a first transistor, a second transistor, an organic light emitting diode, and a capacitor electrically connected to the first thin film transistor. The first transistor includes a first semiconductor pattern below a first interlayer insulation layer and a first control electrode above the first interlayer insulation layer and below a second interlayer insulation layer. The second transistor includes a second control electrode above the first interlayer insulation layer and below the second interlayer insulation layer. A second semiconductor pattern is above the second interlayer insulation layer.

Claims (34)

1. A display device comprising:

a base substrate;

a first transistor above the base substrate and comprising a first source, a first drain, a first semiconductor pattern below a first insulation layer, and a first gate above the first insulation layer and below a second insulation layer;

a second transistor above the base substrate and comprising a second source, a second drain, a second gate above the first insulation layer and below the second insulation layer, a second semiconductor pattern above the second insulation layer and a third gate above the first and the second insulation layers and electrically connected to the second gate;

a third transistor above the base substrate and comprising a third source, a third drain, a third semiconductor pattern below the first insulation layer, and a fourth gate above the first insulation layer and below the second insulation layer;

a light emitting diode above the second insulation layer, and

a capacitor electrically connected to at least one of the first transistor, the second transistor and the third transistor.

2. The display device of claim 1 , wherein the first semiconductor pattern comprises polysilicon semiconductor and the second semiconductor pattern comprises an oxide semiconductor.

3. The display device of claim 2 , wherein the third semiconductor pattern comprises polysilicon semiconductor.

4. The display device of claim 2 , wherein the oxide semiconductor comprises vertical crystals.

5. The display device of claim 1 , further comprise at least one third insulation layer above the second insulation layer.

6. The display device of claim 1 , further comprising a power line to which a first voltage is applied, and

wherein the first transistor is electrically disposed between the power line and the third transistor.

7. The display device of claim 6 , wherein the third transistor is electrically disposed between the first transistor and the light emitting diode.

8. The display device of claim 1 , wherein the second transistor receives a data signal from a data line.

9. The display device of claim 1 , further comprising a scan line to which a scan signal is applied, and

wherein the second transistor is turned on by the scan signal.

10. A display device comprising:

a base substrate;

a first transistor above the base substrate and comprising a first source, a first drain, a first semiconductor pattern below a first insulation layer, and a first gate above the first insulation layer and below a second insulation layer;

a second transistor above the base substrate and comprising a second source, a second drain, a second gate above the first insulation layer and below the second insulation layer, a second semiconductor pattern above the second insulation layer and a third gate above the first and the second insulation layers and electrically connected to the second gate;

a third transistor above the base substrate and comprising a third source, a third drain, a third semiconductor pattern below the first insulation layer, and a fourth gate above the first insulation layer and below the second insulation layer; and

a light emitting diode above the second insulation layer,

wherein one of the first source and the first drain is electrically connected to one of the second source and the second drain.

11. The display device of claim 10 , wherein the first semiconductor pattern comprises polysilicon semiconductor and the second semiconductor pattern comprises an oxide semiconductor.

12. The display device of claim 11 , wherein the third semiconductor pattern comprises polysilicon semiconductor.

13. The display device of claim 11 , wherein the oxide semiconductor comprises vertical crystals.

14. The display device of claim 10 , further comprise at least one third insulation layer above the second insulation layer.

15. The display device of claim 10 , further comprising a power line to which a first voltage is applied, and

wherein the first transistor is electrically disposed between the power line and the third transistor.

16. The display device of claim 15 , wherein the third transistor is electrically disposed between the first transistor and the light emitting diode.

17. The display device of claim 10 , wherein the second transistor receives a data signal from a data line.

18. The display device of claim 10 , further comprising a scan line to which a scan signal is applied, and

wherein the second transistor is turned on by the scan signal.

Priority Claims (1)
KR 10-2016-0113445 · Sep 2, 2016 · national
Continuity (3)
Continuation 16459060 · Jul 1, 2019
Continuation 15657369 · Jul 24, 2017
Related Publication 20200227668A1 · Jul 16, 2020
Cited By (2)
US 12,256,593 US 12,307,964