IP Library Granted Patent US 12,256,593
Granted Patent B2
US 12,256,593 · App. 18/073,870 · Granted Mar 18, 2025

Display device and method of manufacturing the same

Inventors: Jaybum Kim (Seoul, KR); Eoksu Kim (Seoul, KR); Kyoungseok Son (Seoul, KR); Junhyung Lim (Seoul, KR); Jihun Lim (Hwaseong-si, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
H10K50/805G09G3/32G09G3/3233H10B10/125H10K59/1213H10K77/10G09G2300/0426G09G2300/0814G09G2300/0842G09G2300/0861G09G2300/0866G09G2310/0245G09G2310/0262H10K50/30H10K59/1201H10K59/1216H10K71/621
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,256,593
App. No.
18/073,870
Granted
Mar 18, 2025
Kind
B2
Abstract

A display device includes a base substrate, a first transistor, a second transistor, an organic light emitting diode, and a capacitor electrically connected to the first thin film transistor. The first transistor includes a first semiconductor pattern below a first interlayer insulation layer and a first control electrode above the first interlayer insulation layer and below a second interlayer insulation layer. The second transistor includes a second control electrode above the first interlayer insulation layer and below the second interlayer insulation layer. A second semiconductor pattern is above the second interlayer insulation layer.

Claims (36)

1. A display device comprising:

a base substrate;

a first transistor above the base substrate and comprising a first channel area below a first insulation layer and a first gate above the first insulation layer and below a second insulation layer;

a second transistor above the base substrate and comprising a second gate above the first insulation layer and below the second insulation layer, a second channel area above the second insulation layer and a third gate above the first and the second insulation layers and electrically connected to the second gate;

a third transistor above the base substrate and comprising a third channel area below the first insulation layer and a fourth gate above the first insulation layer and below the second insulation layer; and

a light emitting diode above the second insulation layer,

wherein the first transistor is electrically connected to the second transistor through a conductive pattern,

the first transistor is electrically connected to the third transistor, and

the first channel area comprises a polysilicon semiconductor and the second channel area comprises an oxide semiconductor.

2. The display device of claim 1 , wherein the third channel area comprises a polysilicon semiconductor.

3. The display device of claim 1 , wherein the oxide semiconductor comprises vertical crystals.

4. The display device of claim 1 , wherein the conductive pattern is disposed over the second insulation layer.

5. The display device of claim 4 , wherein the first transistor further comprises a first source area and a first drain area,

the second transistor further comprises a second source area and a second drain area, and

the conductive pattern connects one of the first source area and the first drain area to one of the second source area and the second drain area.

6. The display device of claim 5 , wherein the first channel area, the first source area, and the first drain area are formed from a same semiconductor pattern.

7. The display device of claim 5 , further comprise at least one third insulation layer above the second insulation layer, and

the conductive pattern is disposed on the at least one third insulation layer.

8. The display device of claim 7 , wherein the conductive pattern is connected to the one of the first source area and the first drain area via a first through hole defined in the first to third insulation layers, and

the conductive pattern is connected to the one of the second source area and the second drain area via a second through hole defined in the third insulation layer.

9. The display device of claim 1 , further comprising a power line to which a first voltage is applied, and

wherein the first transistor is electrically disposed between the power line and the third transistor.

10. The display device of claim 9 , wherein the third transistor is electrically disposed between the first transistor and the light emitting diode.

11. The display device of claim 1 , further comprising a scan line to which a scan signal is applied, and

wherein the second transistor is turned on by the scan signal.

12. The display device of claim 11 , further comprising a light emitting line to which a control signal is applied, and

wherein the third transistor is turned on by the control signal.

13. The display device of claim 1 , wherein the second transistor is electrically connected to a scan line, and

the third transistor is electrically connected to a light emitting line different from the scan line.

14. The display device of claim 1 , further comprising a power line to which a first voltage is applied, and

wherein he third transistor is electrically disposed between the power line and the first transistor.

15. The display device of claim 1 , wherein the first transistor further comprises a first source area and a first drain area,

the third transistor further comprises a third source area and a third drain area, and

one of the first source and the first drain is electrically connected to one of the third source and the third drain.

16. The display device of claim 15 , wherein the first channel area, the first source area, the first drain area the third channel area, the third source area, and the third drain area are formed from a same semiconductor pattern.

17. The display device of claim 16 , wherein the semiconductor pattern comprises a polysilicon semiconductor.

Priority Claims (1)
KR 10-2016-0113445 · Sep 2, 2016 · national
Continuity (6)
Continuation 17082459 · Oct 28, 2020
Continuation 16911525 · Jun 25, 2020
Continuation 16836005 · Mar 31, 2020
Continuation 16459060 · Jul 1, 2019
Continuation 15657369 · Jul 24, 2017
Related Publication 20230099080A1 · Mar 30, 2023
References Cited (67)
US 7880701B2 · Chang et al. · 2011 [cited by applicant]
US 8067775B2 · Miyairi et al. · 2011 [cited by applicant]
US 8421090B2 · Choi · 2013 [cited by applicant]
US 8455876B2 · Choi et al. · 2013 [cited by applicant]
US 8779416B2 · Kim · 2014 [cited by applicant]
US 9041000B2 · Jeon · 2015 [cited by applicant]
US 9129927B2 · Gupta et al. · 2015 [cited by applicant]
US 9171640B2 · Miyake et al. · 2015 [cited by applicant]
US 9245908B2 · Lee et al. · 2016 [cited by applicant]
US 9577219B2 · Yamazaki et al. · 2017 [cited by applicant]
US 9601052B2 · Jeon · 2017 [cited by applicant]
US 9620534B2 · Yang et al. · 2017 [cited by applicant]
US 9721973B2 · Lee et al. · 2017 [cited by applicant]
US 9806139B2 · Sato · 2017 [cited by applicant]
US 9818765B2 · Osawa et al. · 2017 [cited by applicant]
US 9911762B2 · Yan et al. · 2018 [cited by applicant]
US 9966391B2 · Jin et al. · 2018 [cited by applicant]
US 10340472B2 · Kim et al. · 2019 [cited by applicant]
US 10673008B2 · Kim et al. · 2020 [cited by applicant]
US 10790467B2 · Kim et al. · 2020 [cited by applicant]
US 10854837B2 · Kim et al. · 2020 [cited by applicant]
US 20100019996A1 · You et al. · 2010 [cited by applicant]
US 20110079784A1 · Im · 2011 [cited by applicant]
US 20130168666A1 · Yan et al. · 2013 [cited by applicant]
US 20140098082A1 · Kwon et al. · 2014 [cited by applicant]
US 20140346478A1 · Cho · 2014 [cited by applicant]
US 20140353607A1 · Kim · 2014 [cited by applicant]
US 20150055047A1 · Chang et al. · 2015 [cited by applicant]
US 20150243683A1 · Lee et al. · 2015 [cited by applicant]
US 20160217746A1 · An et al. · 2016 [cited by applicant]
US 20180053791A1 · Sung · 2018 [cited by examiner]
US 20180069190A1 · Kim et al. · 2018 [cited by applicant]
US 20180158846A1 · Umezaki · 2018 [cited by applicant]
US 20180269428A1 · Uchida et al. · 2018 [cited by applicant]
US 20190326543A1 · Kim et al. · 2019 [cited by applicant]
US 20200328369A1 · Kim et al. · 2020 [cited by applicant]
US 20210074944A1 · Kim et al. · 2021 [cited by applicant]
CN 105552083 · 2016 [cited by applicant]
JP 2013012610 · 2013 [cited by applicant]
KR 1020060001345 · 2006 [cited by applicant]
KR 1020070101697 · 2007 [cited by applicant]
KR 1020110021259 · 2011 [cited by applicant]
KR 1020110024935 · 2011 [cited by applicant]
KR 1020110037220 · 2011 [cited by applicant]
KR 101048965 · 2011 [cited by applicant]
KR 101073301 · 2011 [cited by applicant]
KR 1020130023079 · 2013 [cited by applicant]
KR 1020140004386 · 2014 [cited by applicant]
KR 1020140044578 · 2014 [cited by applicant]
KR 1020140144566 · 2014 [cited by applicant]
KR 1020150010523 · 2015 [cited by applicant]
KR 1020150019891 · 2015 [cited by applicant]
KR 1020150051824 · 2015 [cited by applicant]
KR 1020150101394 · 2015 [cited by applicant]
KR 1020150101403 · 2015 [cited by applicant]
KR 1020150101396 · 2015 [cited by applicant]
KR 1020160013473 · 2016 [cited by applicant]
KR 1020160018825 · 2016 [cited by applicant]
KR 101622182 · 2016 [cited by applicant]
Notice of Allowance issued in corresponding U.S. Appl. No. 17/082,379, filed May 11, 2023. [cited by applicant]
Yamazaki, et al., “Research, Development, and Application of Crystalline Oxide Semiconductor”, SID 2012 Digest, pp. 183-186. [cited by applicant]
Kobayashi, et al., “Electrical Characteristics and Short-Channel Effect of C-Axis Aligned Crystal Idium Gallium Zinc Oxide Transistor With Short Channel Length”, Japanese Journal of Applied Physics, 53, 04EF (2014), pp.… [cited by applicant]
Yamazaki, et al., “Future Possibilities of Crystalline Oxide Semiconductor, Especially C-Axis-Aligned Crystalline IGZO”, SID 2015 Digest, pp. 673-676. [cited by applicant]
S. Matsuda, et al., “Channel Length Dependence of Field-Effect Mobility of C-Axis-Aligned Crystalline In—Ga—Zn—O Field-Effect Transistors”, Japanese Journal of Applied Physics, 54, (2015), pp. 041103-1-041103-4. [cited by applicant]
K. Park, et al., “Reliability of Crystalline Indium-Gallium-Zinc-Oxide Thin-Film Transistors Under Bias Stress With Light Illumination”, IEEE Transactions of Electron Devices., vol. 62, No. 9, Sep. 2015, pp. 2900-2905. [cited by applicant]
J. Zhang, et al., “Flexible Indium-Gallium-Zinc-Oxide Schottky Diode Operating Beyond 2.45 GHz”, Nature Communications, Received Oct. 3, 2014, pp. 1-7. [cited by applicant]
Office Action issued in corresponding U.S. Appl. No. 17/082,379, filed Sep. 14, 2022. [cited by applicant]