Three-dimensional memory device containing a replacement buried source line and methods of making the same
An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures. The source-level semiconductor material layer may be electrically isolated from a substrate semiconductor material layer in the substrate by a series connection of two p-n junctions having opposite polarities.
1. A three-dimensional memory device comprising:
a substrate including a stack of a first conductivity type semiconductor layer having a doping of a first conductivity type and a second conductivity type semiconductor layer having a doping of a second conductivity type that is an opposite of the first conductivity type and providing a p-n junction at an interface with a bottom surface of the first conductivity type semiconductor layer;
a source-level semiconductor material layer contacting a top surface of the first conductivity type semiconductor layer and having a doping of the first conductivity type;
an alternating stack of insulating layers and electrically conductive layers overlying semiconductor pillar structures and the source-level semiconductor material layer; and
memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective memory film.
2. The three-dimensional memory device of claim 1 , wherein a lower portion of an outer sidewall of each of the vertical semiconductor channels directly contacts the source-level semiconductor material layer.
3. The three-dimensional memory device of claim 1 , further comprising dielectric layer stacks contacting a bottom surface of a respective one of the vertical semiconductor channels and a respective recessed surface of the first conductivity type semiconductor layer.
4. The three-dimensional memory device of claim 3 , wherein each of the dielectric layer stacks contacts, and is laterally surrounded by, the source-level semiconductor material layer.
5. The three-dimensional memory device of claim 4 , wherein each of the memory films comprises a charge storage layer and a tunneling dielectric layer.
6. The three-dimensional memory device of claim 5 , wherein each of the dielectric layer stacks comprises a tunneling dielectric material portion having a same composition and a same thickness as the tunneling dielectric layer, and a charge storage material portion having a same composition and a same thickness as the charge storage layer.
7. The three-dimensional memory device of claim 1 , wherein a bottommost surface of each of the vertical semiconductor channels directly contacts the source-level semiconductor material layer.
8. The three-dimensional memory device of claim 1 , wherein each of the memory films has a tubular configuration, laterally surrounds and contacts a respective one of the vertical semiconductor channels, and includes a respective vertical stack of memory elements.
9. The three-dimensional memory device of claim 8 , wherein each of the memory films has an annular bottom surface that contact the source-level semiconductor material layer.
10. The three-dimensional memory device of claim 1 , further comprising:
a source region included within the source-level semiconductor material layer, having a doping of the second conductivity type, and laterally spaced from the vertical semiconductor channels;
a backside trench vertically extending through the alternating stack; and
a backside contact via structure located within the backside trench and contacting a top surface of the source region.
11. A method of forming a three-dimensional memory device comprising:
forming a stack of a first conductivity type semiconductor layer having a doping of a first conductivity type and a second conductivity type semiconductor layer having a doping of a second conductivity type that is an opposite of the first conductivity type and providing a p-n junction at an interface with a bottom surface of the first conductivity type semiconductor layer in an upper portion of a substrate;
forming a source-level sacrificial layer over the first conductivity type semiconductor layer;
forming an alternating stack of insulating layers and spacer material layers over the source-level sacrificial layer and semiconductor pillar structures, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;
forming memory stack structures including a respective vertical semiconductor channel and a respective memory film;
forming a source-level cavity by removing the source-level sacrificial layer; and
forming a source-level semiconductor material layer within a volume of the source-level cavity directly on the vertical semiconductor channels and a top surface of the first conductivity type semiconductor layer.
12. The method of claim 11 , further comprising removing portions of the memory films that are physically exposed to the source-level cavity using an isotropic etch process.
13. The method of claim 12 , wherein a lower portion of an outer sidewall of each of the vertical semiconductor channels is physically exposed by the isotropic etch process.
14. The method of claim 13 , wherein the source-level semiconductor material layer is formed directly on the lower portion of the outer sidewall of each of the vertical semiconductor channels.
15. The method of claim 11 , wherein:
the second conductivity type semiconductor layer is formed over a substrate semiconductor material layer that has a doping of the first conductivity type; and
the source-level semiconductor material layer has a doping of the first conductivity type and is electrically isolated from the substrate semiconductor material layer by a series of two p-n junctions having opposite polarities.
16. The method of claim 11 , further comprising forming a dielectric liner layer on a top surface of the first conductivity type semiconductor layer, wherein the source-level sacrificial layer is formed on the dielectric liner layer.
17. The method of claim 16 , further comprising removing the dielectric liner layer and portions of the memory films underlying the alternating stack using an isotropic etch process.
18. The method of claim 1 , further comprising forming a backside trench through the alternating stack by etching through unmasked portions of the alternating stack.
19. The method of claim 18 , further comprising applying an isotropic etchant that etches a material of the source-level sacrificial layer through the backside trench, wherein the source-level cavity is formed upon etching of the source-level sacrificial layer by the isotropic etchant.
20. The method of claim 19 , further comprising:
forming a source region at a bottom portion of the backside trench directly on the source-level semiconductor material layer; and
forming a backside contact via structure on the source region within the backside trench.