Semiconductor device having a uniform and thin silicide layer on an epitaxial source/ drain structure and manufacturing method thereof
In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a first layer containing an amorphous first material by a deposition process directly on a semiconductor layer;
forming a second layer containing a metal second material over the first layer;
forming a third layer containing a third material over the second layer;
performing a thermal process, thereby forming an alloy layer of the amorphous first material and the metal second material, the alloy layer being in direct contact with the third layer; and
after performing the thermal process, removing the third layer, thereby exposing a major surface of the alloy layer, and
after removing the third layer, forming an insulating layer in direct contact with the major surface of the alloy layer.
2. The method of claim 1 , wherein the amorphous first material is amorphous silicon or amorphous germanium.
3. The method of claim 1 , wherein:
the amorphous first material is amorphous silicon, and
the metal second material is at least one of Ti, Co, Ni, W or Ta.
4. The method of claim 1 , wherein the third material is a metal nitride.
5. The method of claim 1 , wherein:
the amorphous first material is amorphous silicon,
the metal second material is Ti, and
the third material is TiN.
6. The method of claim 1 , wherein the thermal process is performed at a temperature of 500° C. to 1000° C.
7. The method of claim 1 , wherein the thermal process is performed for a time period of 1 μsec to 1 msec.
8. The method of claim 1 , wherein a thickness of the first layer is in a range from 1 nm to 10 nm.
9. The method of claim 1 , wherein the alloy layer has a substantially uniform thickness in a range from 1 nm to 10 nm.
10. The method of claim 1 , wherein by the thermal process, the amorphous first material is fully consumed forming the alloy layer.
11. The method of claim 1 , further comprising a cleaning process before forming the second layer.
12. A method of manufacturing a semiconductor device including a Fin FET, the method comprising:
forming a fin structure over a substrate, the fin structure extending in a first direction in plan view,
forming an isolation insulating layer over the substrate so that a lower portion of the fin structure is embedded in the isolation insulating layer and an upper portion of the fin structure is exposed from the isolation insulating layer;
recessing an upper portion of the fin structure;
forming an epitaxial source/drain structure over the recessed fin structure;
forming a silicide layer over at least a part of the epitaxial source/drain structure, wherein:
the forming the silicide layer includes:
forming an amorphous silicon layer over the epitaxial source/drain structure by a deposition process;
forming a Ti layer over the amorphous silicon layer;
forming a TiN layer over the Ti layer; and
performing a thermal process, thereby forming a TiSi layer,
removing at least the TiN layer after the TiSi layer is formed and before forming a first interlayer dielectric layer, and
after removing the TiN layer, forming an etch stop layer in direct contact with a surface of the TiSi layer, from which the TiN layer is removed.
13. The method of claim 12 , further comprising:
before recessing the fin structure, forming a dummy gate structure over a part of the fin structure, the dummy gate structure including a dummy gate electrode and a dummy gate dielectric layer disposed between the dummy gate electrode and the upper portion of the fin structure, the dummy gate structure extending in a second direction crossing the first direction in plan view;
after forming the silicide layer, forming the first interlayer dielectric layer;
after forming the first interlayer dielectric layer, removing the dummy gate structure, thereby forming a gate space in the interlayer dielectric layer;
forming a metal gate structure in the gate space;
forming a second interlayer dielectric layer over the metal gate structure; and
forming a contact plug in contact with the silicide layer of the epitaxial source/drain structure.
14. The method of claim 12 , wherein:
the epitaxial source/drain structure is formed to have a diamond shape over the recessed fin structure.
15. The method of claim 14 , wherein:
the silicide layer is formed to contact at least a top part and a partial bottom part of the epitaxial source/drain structure.
16. The method of claim 1 , wherein:
the remaining metal second material is completely removed when the third layer is completely removed.
17. A method of manufacturing a semiconductor device, the method comprising:
forming a first layer containing an amorphous first material by a deposition process directly on a semiconductor layer over a substrate;
forming a second layer containing a metal second material over the first layer;
forming a third layer containing a third material made of metal nitride over the second layer;
performing a thermal process, thereby forming an alloy layer of the amorphous first material and the metal second material, the alloy layer being in direct contact with the third layer; and
after performing the thermal process, removing the third layer, thereby exposing a major surface of the alloy layer, and
after removing the third layer, forming an insulating layer in direct contact with the major surface of the alloy layer.
18. The method of claim 17 , wherein:
the amorphous first material is amorphous silicon,
the metal second material is Ti, and
the third material is TiN.