Technological method for preventing, by means of buried etch stop layers, the creation of vertical/lateral inhomogeneities when etching through-silicon vias

1. A method for producing a semiconductor device, comprising the steps of:

providing a silicon wafer having a plurality of raised portions of equal height on a first surface of the silicon wafer as a placeholder for through-silicon vias;

depositing an etch stop layer on the first surface of the silicon wafer;

planarizing a surface of the etch stop layer;

using a wafer bonding process to bond a first carrier wafer to the surface of the etch stop layer;

producing components on or in a second surface of the silicon wafer in a front-end-of-line process;

etching a plurality of trenches into the silicon wafer using a masked etching process, proceeding from the second surface of the silicon wafer, each trench being formed at the respective location of one raised portion of the plurality of raised portions;

depositing side wall insulation layers made of insulating material on side walls of the trenches;

forming through-silicon vias by filling the trenches with electrically conductive material;

producing a conductor path stack in a back-end-of-line process for contacting the active components on the second surface of the silicon wafer;

temporarily bonding a second carrier wafer onto a surface of the conductor path stack;

removing the first carrier wafer; and

exposing the through-silicon vias by partially removing the etch stop layer.

2. The method according to claim 1 , comprising, after the step of exposing the through-silicon vias, the additional steps of:

depositing a metallization layer on the etch stop layer;

structuring the metallization layer; and

debonding the second carrier wafer.

3. The method according to claim 2 , wherein the silicon wafer and/or the first carrier wafer is thinned before the active components are produced.

4. The method according to claim 3 , in which the silicon wafer is set to a final thickness for the semiconductor device by thinning the silicon wafer.

5. The method according to claim 2 , in which the step of providing the silicon wafer having a plurality of raised portions of equal height on a first surface of the silicon wafer as a placeholder for through-silicon vias comprises the steps of:

providing the silicon wafer; and

then producing the plurality of raised portions of equal height on the first surface of the silicon wafer.

6. The method according to claim 5 , in which the plurality of raised portions is produced using an etching process.

7. The method according to claim 1 , in which at least one raised portion of the plurality of raised portions is produced with a geometry selected from a cylinder, a cuboid or a square.

8. The method according to claim 1 , in which at least two raised portions of the plurality of raised portions are produced with different geometries.

9. The method according to claim 1 , in which the silicon wafer is diced into single chips after debonding the second carrier wafer.

10. The method according to claim 1 , wherein the silicon wafer and/or the first carrier wafer is thinned before the active components are produced.

11. The method according to claim 10 , in which the silicon wafer is set to a final thickness for the semiconductor device by thinning the silicon wafer.

12. The method according to claim 1 , in which the step of providing a silicon wafer having a plurality of raised portions of equal height on a first surface of the silicon wafer as a placeholder for through-silicon vias comprises the steps of:

providing the silicon wafer; and

then producing the plurality of raised portions of equal height on the first surface of the silicon wafer.