Semiconductor die contact structure and method
A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.
1. A semiconductor device comprising:
a metal contact over a substrate, the metal contact having a thickness of at least 15,000 Å, wherein a first material is located throughout the metal contact;
a first passivation layer located at least partially over the metal contact;
a polyimide layer located over the first passivation layer, the polyimide layer extending through the first passivation layer to make physical contact with the metal contact; and
an external contact in physical contact with the metal contact, the external contact extending through the polyimide layer and the first passivation layer, the external contact being a single continuous conductive material.
2. The semiconductor device of claim 1 , wherein the metal contact has a thickness of about 20,000 Å.
3. The semiconductor device of claim 1 , wherein the polyimide layer has a thickness of between about 2.5 μm and about 12 μm.
4. The semiconductor device of claim 1 , further comprising a protective layer covering sidewalls of the external contact.
5. The semiconductor device of claim 4 , wherein the protective layer comprises tin.
6. The semiconductor device of claim 5 , wherein the protective layer has a thickness of between about 500 Å and about 2,000 Å.
7. The semiconductor device of claim 1 , wherein the external contact has a thickness of less than about 60 μm.
8. A semiconductor device comprising:
a plurality of extra low-k dielectric layers over a semiconductor substrate;
a buffer contact located over the plurality of extra low-k dielectric layers, the buffer contact being at least 15,000 Å in thickness;
a first dielectric layer extending over the buffer contact;
a polyimide layer over the first dielectric layer; and
a conductive pillar extending through the polyimide layer to make physical contact with the buffer contact, the conductive pillar being an external contact, the conductive pillar being a single continuous conductive material.
9. The semiconductor device of claim 8 , wherein the conductive pillar has a thickness of less than about 60 μm.
10. The semiconductor device of claim 8 , wherein the conductive pillar has a width of between about 10 μm and about 200 μm.
11. The semiconductor device of claim 8 , further comprising a conductive barrier layer over the conductive pillar.
12. The semiconductor device of claim 11 , wherein the conductive barrier layer comprises nickel.
13. The semiconductor device of claim 11 , wherein the conductive barrier layer comprises tin.
14. A semiconductor device comprising:
a single metal material over an extra low-k dielectric layer, the single metal material having a first width and a first thickness, the first thickness being greater than 15,000 Å;
a first passivation layer located over the single metal material;
a second passivation layer located over the first passivation layer;
a first conductive pillar extending through both the second passivation layer and the first passivation layer to make physical contact with the single metal material, wherein the first conductive pillar has a first width adjacent to the first passivation layer and a second width larger than the first width; and
a protective layer covering a top surface and sidewalls of the first conductive pillar, the protective layer meets the second passivation layer at the first conductive pillar.
15. The semiconductor device of claim 14 , wherein the first conductive pillar has a thickness of less than about 60 μm.
16. The semiconductor device of claim 15 , wherein the first conductive pillar has a thickness of between about 30 μm and about 50 μm.
17. The semiconductor device of claim 16 , wherein the first conductive pillar is a copper pillar.
18. The semiconductor device of claim 14 , wherein the protective layer has a thickness between 500 Å and 5000 Å.
19. The semiconductor device of claim 18 , wherein the protective layer has a thickness between 500 Å and 2000 Å.
20. The semiconductor device of claim 14 , wherein the extra low-k dielectric layer is over an active layer of a silicon-on-insulator substrate.