Apparatuses and/or methods for operating a memory cell as an anti-fuse
Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.
1. A method comprising:
selecting a memory cell for time programmable operation, the memory cell operable for storing one of a plurality of reprogrammable states; and
applying a bias to the memory cell based at least in part on the selecting, wherein applying the bias forms a resistance path in the memory cell corresponding to a one-time programmable state of the memory cell that is different than the plurality of reprogrammable states.
2. The method of claim 1 , further comprising:
determining a logic state for the one-time programmable operation; and
determining a direction of the bias based at least in part on the determined logic state.
3. The method of claim 1 , wherein the bias is greater than biasing associated with programming the plurality of reprogrammable states.
4. The method of claim 1 , wherein forming the resistance path comprises operating the memory cell as an anti-fuse.
5. The method of claim 1 , wherein forming the resistance path comprises operating the memory cell as a fuse.
6. The method of claim 1 , wherein forming the resistance path comprises forming a metallic path in the memory cell.
7. The method of claim 1 , wherein forming the resistance path comprises forming a void in the memory cell.
8. A memory device, comprising:
a memory cell operable to store one of a plurality of reprogrammable states; and
a selector operable to form a resistance path in the memory cell corresponding to a one-time programmable state of the memory cell that is different than the plurality of reprogrammable states.
9. The memory device of claim 8 , wherein, to form the resistance path corresponding to the one-time programmable state, the selector is operable to form a metallic path in the memory cell.
10. The memory device of claim 9 , wherein the selector is operable to form the metallic path based at least in part on ion migration from a metal plug of the memory cell.
11. The memory device of claim 8 , wherein, to form the resistance path corresponding to the one-time programmable state, the selector is operable to form a void in the memory cell.
12. The memory device of claim 8 , wherein, to form the resistance path corresponding to the one-time programmable state, the selector is operable to apply a bias having a direction that is based at least on part on the one-time programmable state.
13. The memory device of claim 8 , wherein, to form the resistance path corresponding to the one-time programmable state, the selector is operable to apply a bias current to the memory cell.
14. A memory device, comprising:
a memory array including a plurality of memory cells that are each operable to store one of a plurality of reprogrammable states;
a first selector configured for providing a first bias, the first bias to form a first resistance path in a first memory cell that corresponds to a first one-time programmable state that is different than the plurality of reprogrammable states; and
a second selector configured for providing a second bias, the second bias to form a second resistance path in a second memory cell corresponding to a second one-time programmable state that is different than the first one-time programmable state and different than the plurality of reprogrammable states.
15. The memory device of claim 14 , wherein the first selector is configured for providing a forward bias current through the first memory cell, and the second selector is configured for providing a reverse bias current through the second memory cell.
16. The memory device of claim 14 , wherein the first selector is configured for forming a metallic path through the first memory cell, and the second selector is configured for forming a void through the second memory cell.
17. The memory device of claim 14 , wherein the first selector is configured for operating the first memory cell as an anti-fuse, and the second selector is configured for operating the second memory cell as a fuse.
18. The memory device of claim 14 , wherein each memory cell of the plurality comprises a metal plug for forming the first resistance path, the second resistance path, or both.
19. The memory device of claim 14 , wherein each memory cell of the plurality comprises a chalcogenide material.
20. The memory device of claim 14 , wherein the first bias, the second bias, or both, are higher than biasing employed for writing the plurality of reprogrammable states.