Wordline voltage overdrive methods and systems
A methodology and structure for performing an erase verify in non-volatile memory is described. Both the odd wordlines and the even wordlines are driven to a high voltage level. This can be done simultaneously. The simultaneous charging of both the odd wordlines and the even wordlines, even when the erase verify will occur on only one of the odd or even wordlines reduces RC delay in the charging of the wordlines. After the odd and even wordlines are charged, then one set of wordlines, either the odd or even wordlines, is dropped to the erase verify voltage. The erase sense operation is then performed.
1. An erase verify method for non-volatile memory, comprising:
driving both a plurality of odd wordlines and a plurality of even wordlines to a high voltage;
ramping a verify one of the plurality of odd wordlines and the plurality of even wordlines to a verify target voltage that is less than the high voltage;
holding a non-verify one of the plurality of odd wordlines and the plurality of even wordlines at the high voltage; and
performing an erase verify on the verify one of the plurality of odd wordlines and the plurality of even wordlines.
2. The method of claim 1 , wherein the driving both the plurality of odd wordlines and the plurality of even wordlines to the read voltage operates to reduce capacitive delays in electrical signal propagation along both the plurality of odd wordlines and the plurality of even wordlines with adjacent wordlines being driven to a same voltage at a same time.
3. The method of claim 1 , wherein the driving both the plurality of odd wordlines and the plurality of even wordlines to the read voltage includes driving the read voltage from a near, first end to a far, second end of the wordlines over a drive time period.
4. The method of claim 3 , wherein ramping a verify one of the plurality of odd wordlines and the plurality of even wordlines includes ramping after the drive time period.
5. The method of claim 4 , wherein ramping includes reducing voltage at the second end to an order of magnitude less than the read voltage.
6. The method of claim 3 , wherein performing an erase verify includes performing the sensing after the target voltage is reached at the second end.
7. The method of claim 3 , wherein ramping continues until the target voltage is reached at the second end.
8. The method of claim 7 , wherein performing an erase verify includes performing the sensing after the target voltage is reached at the second end.
9. The method of claim 1 , wherein driving includes synchronizing the driving of the plurality of odd wordlines and the plurality of even wordlines to the read voltage.
10. The method of claim 1 , wherein driving includes driving to the read voltage of greater than five volts.
11. The method of claim 10 , wherein ramping includes ramping from the read voltage to a target voltage of less than one volt.
12. The method of claim 1 , wherein the driving both the plurality of odd wordlines and the plurality of even wordlines to the read voltage minimizes wordline coupling between adjacent odd and even wordlines.
13. The method of claim 1 , further comprising applying a negative bitline pulse to the program bitline during a start of a precharge of a program bitline during a programming.