Techniques for faster ramp-up times for unselected word lines in non-volatile memory
In a non-volatile memory array such as a NAND memory, when a word line of a block is selected for a read or write, the selected word line is biased at one level through one decoding path, while the unselected word lines of a block are biased at a different level though another decoding path. For memory operations, such as leakage detection, in which all of the word lines are biased with the same level, such as an unselected voltage level, the selected word line decoding path is otherwise unused. To increase the speed with which word lines can be ramped-up, for operation that bias all of the word lines of a block at the unselected level, both of the decoding paths can be used concurrently to reduce ramp-up times.
1 . A non-volatile memory system, comprising:
a control circuit configured to connect to an array of non-volatile memory cells connected along a plurality of word lines, the control circuit comprising:
charge pump circuitry configured to generate a first word line bias voltage;
decoding circuitry configured to selectively connect the charge pump circuitry to the plurality of word lines, comprising a first decoding path between the charge pump circuitry and a first group of the plurality of word lines and a second decoding path between the charge pump circuitry and the first group of word lines:
a word line selection circuit through which the decoding circuitry is connected to the first group of word lines; and
a level shifter circuit configured to receive a logic level control signal and generate therefrom a high voltage control signal for the word line selection circuit, the level shifter circuit comprising a first NMOS transistor connected between the logic level control signal and a high voltage control signal for the word line selection circuit and a PMOS transistor having a gate connected to receive an inverse of the logic level control signal, the control circuit configured to:
in a first decoding mode, supply the first group of word lines with the first word line bias voltage by the first, but not the second, decoding path;
in a second decoding mode, concurrently supply the first group of word lines with the first word line bias voltage by the first decoding path and the second decoding path; and
maintain a gate voltage for the first NMOS transistor at a high value for the logic level control signal while the logic level control signal is asserted.
2 . The non-volatile memory system of claim 1 , wherein the control circuit is formed on a control die, the non-volatile memory system further comprising:
a memory die including the array, the memory die separate from and bonded to the control die.
3 . The non-volatile memory system of claim 1 , wherein the control circuit is further configured to:
receive a first command; and
select either the first decoding mode or the second decoding mode based on the first command.
4 . The non-volatile memory system of claim 3 , wherein the array of non-volatile memory cells comprises a plurality of blocks of the memory cells having a NAND architecture, the first group of word lines including word lines corresponding to a first block of the plurality of blocks of the memory cells, wherein the control circuit is further configured to:
in response to the first command specifying an access of a selected word line of the first block, select the first decoding mode for biasing unselected word lines of the first block.
5 . The non-volatile memory system of claim 4 , wherein the control circuit is further configured to:
in response to the first command specifying an access of a selected word line of the first block, bias the selected word line of the first block by the second decoding path.
6 . The non-volatile memory system of claim 4 , wherein the first command specifies a read of the selected word line of the first block.
7 . The non-volatile memory system of claim 4 , wherein the first command specifies a write of the selected word line of the first block.
8 . The non-volatile memory system of claim 3 , wherein the array of non-volatile memory cells comprises a plurality of blocks of the memory cells having a NAND architecture, the first group of word lines including word lines corresponding to a first of the plurality of blocks of the memory cells, wherein the control circuit is further configured to:
in response to the first command specifying all of the word lines of the first block being biased at a common bias level, select the second decoding mode for biasing all of the word lines of the first block.
9 . The non-volatile memory system of claim 8 , wherein the first command specifies a leak detection operation for the first block.
10 . The non-volatile memory system of claim 8 , wherein the first command specifies a refresh operation for the first block.
11 . The non-volatile memory system of claim 8 , wherein the first command specifies a pre-program operation for the first block.
12 . The non-volatile memory system of claim 1 wherein the level shifter circuit further comprises:
a second NMOS transistor having a gate connected to the high voltage control signal for the word line selection circuit and connected between a high voltage supply level and, though the PMOS transistor, the high voltage control signal for the word line selection circuit.
13 . A method, comprising:
receiving a command to perform an operation on a first group of word lines of an array of non-volatile memory cells;
based on the command, selecting either a first decoding mode or a second decoding mode for biasing the first group of word lines from a charge pump circuit by a decoding circuitry having a first decoding path and a second decoding path, the decoding circuitry being connected to the first group of word lines through a word line selection circuit;
in response to selecting the first decoding mode, biasing the first group of word lines from the charge pump circuit through the first decoding path, but not through the second decoding path; and
in response to selecting the second decoding mode, biasing the first group of word lines from the charge pump through the first decoding path and the second decoding path concurrently, where biasing the first group of word lines includes:
receiving a logic level control signal at a level shifter circuit comprising a first NMOS transistor connected between the logic level control signal and a high voltage control signal for the word line selection circuit and a PMOS transistor having a gate connected to receive an inverse of the logic level control signal; and
generating by the level shifter circuit from the logic level control signal of a high voltage control signal for the word line selection circuit, including maintaining a gate voltage for the first NMOS transistor at a high value for the logic level control signal while the logic level control signal is asserted.
14 . The method of claim 13 , wherein the array of non-volatile memory cells comprises a plurality of blocks of the memory cells having a NAND architecture, the first group of word lines including word lines corresponding to a first of the plurality of blocks of the memory cells, and wherein selecting either the first decoding mode or the second decoding mode comprises:
determining whether the command specifies an access of a selected word line of the first block; and
in response to the command specifying the access of the selected word line, selecting the first decoding mode for biasing unselected word lines of the first block.
15 . The method of claim 14 , wherein selecting either the first decoding mode or the second decoding mode further comprises:
in response to the command specifying the access of the selected word line, biasing the selected word line by the second decoding path.
16 . The method of claim 13 , wherein the array of non-volatile memory cells comprises a plurality of blocks of the memory cells having a NAND architecture, the first group of word lines including word lines corresponding to a first of the plurality of blocks of the memory cells, and wherein selecting either the first decoding mode or the second decoding mode comprises:
determining whether the command specifies that all of the word lines of the first block being biased at a common bias level; and
in response to the command specifying all of the word lines of the first block being biased at the common bias level, selecting the second decoding mode for biasing all of the word lines of the first block.
17 . A non-volatile memory system, comprising:
an array including a plurality of non-volatile memory cells connected along a first group of word lines; and
one or more control circuits connected to the array, comprising:
a voltage supply circuit;
decoding and driver circuitry configured to bias the first group of word lines by way of a first bias path and a second bias path;
a word line selection circuit through which the decoding and driver circuitry is connectable to the first group of word lines; and
a level shifter circuit comprising a first NMOS transistor connected between the logic level control signal and a high voltage control signal for the word line selection circuit and a PMOS transistor having a gate connected to receive an inverse of the logic level control signal,
the one or more control circuits configured to:
receive a command to perform an operation on the first group of word lines;
based on the command, select either a first decoding mode or a second decoding mode for biasing the first group of word lines from the voltage supply circuit;
in response to selecting the first decoding mode, bias the first group of word lines from the voltage supply circuit through the first bias path, but not through the second bias path; and
in response to selecting the second decoding mode, bias the first group of word lines from the voltage supply circuit through the first bias path and the second decoding path concurrently, where biasing the first group of word lines includes:
receiving a logic level control signal at a level shifter circuit comprising a first NMOS transistor connected between the logic level control signal and a high voltage control signal for the word line selection circuit and a PMOS transistor having a gate connected to receive an inverse of the logic level control signal; and
generating by the level shifter circuit from the logic level control signal of a high voltage control signal for the word line selection circuit, including maintaining a gate voltage for the first NMOS transistor at a high value for the logic level control signal while the logic level control signal is asserted.
18 . The non-volatile memory system of claim 17 , wherein the array of non-volatile memory cells comprises a plurality of blocks of the memory cells having a NAND architecture, the first group of word lines including word lines corresponding to a first block of the plurality of blocks of the memory cells, and wherein, to select either the first decoding mode or the second decoding mode, the one or more control circuits are configured to:
determine whether the command specifies an access of a selected word line of the first block;
in response to the command specifying the access of the selected word line, select the first decoding mode for biasing unselected word lines of the first block; and
in response to the command not specifying the access of the selected word line, select the second decoding mode for biasing all of the word lines of the first block.
19 . The non-volatile memory system of claim 17 , wherein the one or more control circuits are further configured to:
receive a first command; and
select either the first decoding mode or the second decoding mode based on the first command.
20 . The non-volatile memory system of claim 19 , wherein the array of non-volatile memory cells comprises a plurality of blocks of the memory cells having a NAND architecture, the first group of word lines including word lines corresponding to a first block of the plurality of blocks of the memory cells, wherein the one or more control circuits are further configured to:
in response to the first command specifying an access of a selected word line of the first block, select the first decoding mode for biasing unselected word lines of the first block.