Signal reduction in a microcontroller architecture for non-volatile memory

1. An apparatus comprising:

a memory structure comprising non-volatile memory cells;

a first processor configured to execute first instructions to generate first control signals on a first number of first physical signal lines to control voltages applied to the memory structure by a first circuit to perform memory operations on the non-volatile memory cells;

a second processor configured to execute second instructions to generate second control signals to control a second circuit to sense a condition of the non-volatile memory cells in response to the applied voltages; and

a conversion circuit comprising a plurality of registers coupled by the first physical signal lines to the first processor to receive the first control signals, the conversion circuit configured to convert the first control signals to converted control signals that are output from the conversion circuit on a second number of second physical signal lines to the first circuit, the first number less than the second number to reduce the first number of first physical signal lines coupled between the first processor and the first circuit.

2. The apparatus of claim 1 , wherein the conversion circuit comprises a serial-in and parallel-out pipeline circuit.

3. The apparatus of claim 1 , wherein the conversion circuit comprises a two-stage pipeline structure.

4. The apparatus of claim 1 , wherein the conversion circuit comprises a pre-fetch circuit coupled to a fetch circuit.

5. The apparatus of claim 1 , wherein the first control signals comprise signals controlling timing of voltages applied by the first circuit to the memory structure.

6. The apparatus of claim 1 , wherein the first processor is further configured to arrange the first physical signal lines into groups of first control signals, and provide the first control signals one group at a time on the first physical signal lines.

7. The apparatus of claim 1 , wherein the apparatus further comprises an integrated circuit comprising a first level comprising the memory structure, and a second level comprising the first processor and the second processor, wherein the first level and second level comprise different levels.

8. The apparatus of claim 1 , wherein the memory structure comprises a plurality of memory planes, each comprising the first circuit.

9. The apparatus of claim 1 , wherein the first processor and the second processor are disposed under the memory structure.

10. An apparatus comprising:

a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, and a voltage source circuit configured to apply voltages to the word lines and the bit lines; and

a microcontroller circuit comprising:

a first control circuit configured to:

provide a plurality of first control signals at a first plurality of physical signal lines to the voltage source circuit, wherein the first control signals control timing of memory operations performed on the plurality of memory cells; and

implement a serial-in and parallel-out pipeline to reduce a number of the first plurality of physical signal lines; and

a second control circuit configured to provide a plurality of second control signals to control a second circuit to sense a condition of the plurality of memory cells in response to the memory operations performed on the plurality of memory cells.

11. The apparatus of claim 10 , wherein the serial-in and parallel-out pipeline comprises a two-stage pipeline structure.

12. The apparatus of claim 10 , wherein the serial-in and parallel-out pipeline comprises a pre-fetch circuit coupled to a fetch circuit.

13. The apparatus of claim 10 , wherein the serial-in and parallel-out pipeline comprises a first plurality of shift registers coupled to a second plurality of shift registers.

14. The apparatus of claim 10 , wherein the second circuit comprises data latch circuits.

15. The apparatus of claim 10 , wherein the plurality of memory cells comprise a plurality of memory planes, each coupled to the first plurality of physical signal lines.

16. The apparatus of claim 10 , wherein the controller circuit is disposed under the memory core circuit.

17. A method comprising:

providing a microcontroller coupled to a plurality of memory cells, the microcontroller comprising a first processor and a second processor;

executing a first set of instructions on the first processor to provide first control signals over a plurality of first physical signal lines to a first circuit configured to apply voltages to the plurality of memory cells;

executing a second set of instructions on the second processor to provide second control signals to a second circuit configured to sense a memory state of the plurality of memory cells;

reducing a number of the first physical signal lines by:

storing first control signal data from the first physical signal lines in a first set of registers;

shifting the stored first control signal data from the first set of registers to a second set of registers; and

providing the first control signal data from the second set of registers over second physical signal lines to the first circuit.

18. The method of claim 17 , further comprising implementing a serial-in and parallel-out pipeline to reduce the number of first physical signal lines in the memory circuit.

19. A system comprising:

a memory structure comprising non-volatile memory cells;

a first circuit comprising a voltage generator connected to the memory structure;

a state machine configured to generate first control signals coupled via physical signal lines to the first circuit to control voltages applied to the memory structure by the voltage generator to perform memory operations on the non-volatile memory cells;

a second circuit configured to generate second control signals coupled to a a second circuit configured to sense a condition of the non-volatile memory cells in response to the applied voltage; and

a conversion circuit comprising a two-stage pipeline structure coupled between the state machine and the first circuit, the two-stage pipeline structure configured to reduce a number of the physical signal lines.

20. The system of claim 19 , wherein the plurality of memory die comprise a plurality of memory planes, each coupled to the physical signal lines.