IP Library Granted Patent US 10,957,579
Granted Patent B2
US 10,957,579 · App. 16/530,075 · Granted Mar 23, 2021

Integrated circuit devices including a via and methods of forming the same

Inventors: Yung Bae Kim (Seoul, KR); Harsono Simka (Saratoga, CA); Jong Hyun Lee (Suwon-si, KR)
H01L21/76802H01L21/76829H01L21/76843H01L21/76868
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Quick Facts
Patent No.
US 10,957,579
App. No.
16/530,075
Granted
Mar 23, 2021
Kind
B2
Abstract

Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a first conductive layer on a substrate and selectively forming a second insulating layer on the first insulating layer. The first insulating layer may include a recess, and the first conductive layer may be in the recess of the first insulating layer. The second insulating layer may include a first opening exposing a surface of the first conductive layer. The methods may also include forming a third insulating layer on the second insulating layer and the first conductive layer, forming a second opening extending through the third insulating layer and exposing the first conductive layer, and forming a second conductive layer in the second opening.

Claims (45)

1. A method of forming an integrated circuit device, the method comprising:

forming a first insulating layer and a first conductive layer on a substrate, the first insulating layer comprising a recess, and the first conductive layer being in the recess of the first insulating layer;

selectively forming a second insulating layer on the first insulating layer, the second insulating layer comprising a first opening exposing a surface of the first conductive layer;

forming a third insulating layer on the second insulating layer and the first conductive layer;

forming a second opening extending through the third insulating layer and exposing the first conductive layer; and

forming a second conductive layer in the second opening,

wherein forming the first conductive layer comprises forming a diffusion barrier layer and a first core conductive layer, and

wherein the method further comprises removing an upper portion of the diffusion barrier layer before forming the third insulating layer.

2. The method of claim 1 , further comprising removing an upper portion of the first conductive layer before forming the third insulating layer.

3. The method of claim 2 , wherein removing the upper portion of the first conductive layer is performed before selectively forming the second insulating layer.

4. The method of claim 1 , wherein removing the upper portion of the diffusion barrier layer is performed before selectively forming the second insulating layer, and

wherein selectively forming the second insulating layer comprises forming a portion of the second insulating layer in a space from which the upper portion of the diffusion barrier layer is removed.

5. The method of claim 1 , further comprising forming an etch stop layer on the second insulating layer before forming the third insulating layer.

6. The method of claim 1 , wherein the second conductive layer contacts the first conductive layer.

7. The method of claim 6 , wherein an upper surface of the substrate is closer to a lowermost end of the second conductive layer than a lowermost end of the second insulating layer.

8. A method of forming an integrated circuit device, the method comprising:

forming a first insulating layer and a first conductive layer on a substrate, the first insulating layer comprising a recess, and the first conductive layer being in the recess of the first insulating layer;

forming a blocking layer on the first conductive layer, the blocking layer exposing a surface of the first insulating layer;

forming a second insulating layer on the first insulating layer, the second insulating layer exposing a surface of the blocking layer;

removing the blocking layer to form an opening in the second insulating layer;

forming a third insulating layer on the second insulating layer and the first conductive layer after removing the blocking layer; and

forming a second conductive layer extending through the third insulating layer, the second conductive layer contacting the first conductive layer.

9. The method of claim 8 , wherein the blocking layer contacts an entirety of an upper surface of the first conductive layer.

10. The method of claim 8 , wherein the first insulating layer comprises a material that the second insulating layer comprises.

11. The method of claim 8 , further comprising removing an upper portion of the first conductive layer before forming the third insulating layer.

12. The method of claim 11 , wherein removing the upper portion of the first conductive layer is performed before forming the blocking layer.

13. The method of claim 8 , wherein forming the first conductive layer comprises forming a diffusion barrier layer and a first core conductive layer; and

wherein the method further comprises removing an upper portion of the diffusion barrier layer before forming the third insulating layer.

14. The method of claim 13 , wherein removing the upper portion of the diffusion barrier layer is performed before forming the blocking layer, and

wherein forming the second insulating layer comprises forming a portion of the second insulating layer in a space from which the upper portion of the diffusion barrier layer is removed.

15. The method of claim 8 , wherein the first conductive layer comprises Cu, Co, Ru, Mo, Mn, and/or Nb.

16. A method of forming an integrated circuit device, the method comprising:

forming a first insulating layer and a first conductive layer on a substrate, the first insulating layer comprising a recess, the first conductive layer being in the recess of the first insulating layer, and the first insulating layer exposing an upper surface of the first conductive layer;

removing an upper portion of the first conductive layer;

selectively forming a second insulating layer on the first insulating layer, wherein the first insulating layer and the second insulating layer comprise an opening exposing a surface of the first conductive layer that remains after removing the upper portion of the first conductive layer, and the opening exposes a sidewall of the first insulating layer and a sidewall of the second insulating layer;

forming a third insulating layer on the second insulating layer and the first conductive layer; and

forming a second conductive layer extending through the third insulating layer to contact the first conductive layer.

17. The method of claim 16 , wherein selectively forming the second insulating layer comprises:

forming a blocking layer on the first conductive layer, the blocking layer exposing a surface of the first insulating layer;

forming the second insulating layer on the first insulating layer, the second insulating layer exposing a surface of the blocking layer; and

removing the blocking layer.

18. The method of claim 17 , wherein the blocking layer contacts the first conductive layer, and

wherein the second insulating layer contacts the first insulating layer.

19. The method of claim 16 , wherein removing the upper portion of the first conductive layer is performed before selectively forming the second insulating layer.

20. The method of claim 1 , wherein the first opening comprises an upper portion, and the first opening further comprises a lower portion that exposes a sidewall of the first insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2019
From: KIM, YUNG BAE; SIMKA, HARSONO; LEE, JONG HYUN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 049941/0812 →
Continuity (2)
Provisional Application 62756246 · Nov 6, 2018
Related Publication 20200144103A1 · May 7, 2020
Cited By (2)
US 12,387,977 US 12,476,146