Semiconductor package including stacked semiconductor chips

1. A semiconductor package comprising:

a substrate;

a first interposer disposed over the substrate;

a first chip stack disposed on the substrate on one side of the first interposer, wherein the first chip stack comprises a plurality of first semiconductor chips stacked with an offset in a first direction;

a second chip stack disposed on the first chip stack, wherein the second chip stack comprises a plurality of second semiconductor chips stacked with an offset in a second direction opposite to the first direction; and

a third chip stack disposed on the substrate on an other side of the first interposer, wherein the third chip stack comprises a plurality of third semiconductor chips stacked with an offset in the second direction,

wherein the first interposer is contacted by a bottom surface of the second chip stack that protrudes beyond the first chip stack in the first direction,

wherein the third chip stack has a thickness larger than the sum of thicknesses of the first and second chip stacks, and

wherein the third chip stack extends over at least a portion of the first interposer so that the at least a portion of the first interposer is located in a space under the third chip stack.

2. The semiconductor package of claim 1 , wherein the first interposer is electrically connected between the second chip stack and the substrate.

3. The semiconductor package of claim 2 , wherein the first chip stack is electrically connected to the substrate through a first inter-connector located on the one side of the first chip stack, corresponding to the opposite side of the other side of the first chip stack, wherein the other side of the first chip stack is closer to the first interposer, and

the third chip stack is electrically connected to the substrate through a third inter-connector located on the other side of the third chip stack, wherein the other side of the third chip stack is opposite to the one side of the third chip stack, wherein the one side of the third chip stack is closer to the first interposer.

4. The semiconductor package of claim 1 , wherein the first interposer has the same thickness as the first chip stack.

5. The semiconductor package of claim 1 , further comprising a fourth chip stack disposed on the third chip stack, wherein the fourth chip stack comprises a plurality of fourth semiconductor chips stacked with an offset in the first direction.

6. The semiconductor package of claim 5 , further comprising:

a third interposer contacted by a bottom surface of the fourth chip stack that protrudes beyond the third chip stack in the second direction; and

a second interposer disposed between the third interposer and the first interposer.

7. The semiconductor package of claim 6 , wherein the third chip stack has a thickness equal to the sum of thicknesses of the first, second, and third interposers.

8. The semiconductor package of claim 6 , wherein:

the first interposer is electrically connected between the second chip stack and the substrate and electrically connected between the second interposer and the substrate;

the second interposer is electrically connected between the first interposer and the third interposer; and

the fourth chip stack is electrically connected to the substrate through the third interposer, the second interposer, and the first interposer.

9. The semiconductor package of claim 8 , wherein the first interposer comprises:

a one-side first through via structure disposed on a side relatively close to the second chip stack, wherein the second chip stack and the substrate are electrically connected through the one-side first through via structure; and

an other-side first through via structure disposed on a side relatively far from the second chip stack, wherein the second interposer and the substrate are electrically connected through the other-side first through via structure,

wherein the second interposer comprises:

a second connection terminal electrically connected to the other-side first through via structure; and

a first dummy pattern formed in a region where the one-side first through via structure is not formed.

10. The semiconductor package of claim 9 , wherein the widths of the first and second interposers in a third direction perpendicular to the first and second directions are larger than a width of the first chip stack, such that the first and second interposers have an end which does not overlap the first chip stack, and

the first dummy pattern is disposed between the first and second interposers at the end.

11. The semiconductor package of claim 9 , wherein the second interposer comprises:

a second through via structure; and

a first redistribution layer suitable for electrically connecting the second through via structure to the other-side first through via structure.

12. The semiconductor package of claim 11 , wherein the third interposer comprises:

a third through via structure; and

a second redistribution layer suitable for electrically connecting the third through via structure to the second through via structure.

13. The semiconductor package of claim 6 , wherein the second interposer has a thickness equal to or less than a value obtained by subtracting the thickness of the first chip stack from the sum of thicknesses of the first and second chip stacks.

14. The semiconductor package of claim 6 , wherein the third interposer extends over a top surface of the second chip stack.

15. The semiconductor package of claim 14 , wherein the third interposer comprises a second dummy pattern configured to support the third interposer on the top surface of the second chip stack.

16. The semiconductor package of claim 6 , wherein:

the first and second interposers have sidewalls which are aligned with each other in the first and second directions; and

the third interposer has a sidewall which is not aligned with the aligned sidewalls of the first and second interposers.

17. The semiconductor package of claim 1 , wherein:

the first, second, and third semiconductor chips are the same types of memory chips;

the first and second semiconductor chips have the same thickness; and

the third semiconductor chips have a larger thickness than the thickness of the first and second semiconductor chips.

18. The semiconductor package of claim 5 , wherein:

the first, second, third, and fourth semiconductor chips are the same types of memory chips;

the first, second, and fourth semiconductor chips have the same thickness; and

the third semiconductor chips have a larger thickness than the thickness of the first, second, and fourth semiconductor chips.