Semiconductor package
Provided is a semiconductor package including a package substrate including a substrate pad, a first chip stacked structure including a first base chip mounted on an upper surface of the package substrate, and one or more first stacked chips sequentially offset-stacked along a first direction on the first base chip, a second chip stacked structure including a second base chip offset-stacked along the first direction on an upper surface of the first chip stacked structure, and one or more second stacked chips sequentially offset-stacked along the first direction on the second base chip, a bonding wire, and a first support mounted on the package substrate to be spaced apart from the first chip stacked structure in the first direction and supporting the second chip stacked structure, wherein the first support supports the second chip stacked structure by supporting a lower surface of the second base chip.
1 . A semiconductor package comprising:
a package substrate including a substrate pad;
a first chip stacked structure comprising first chips including a first base chip mounted on an upper surface of the package substrate, and one or more first stacked chips sequentially offset-stacked on the first base chip such that each of the first stacked chips protrudes beyond a side surface of an adjacent lower first chip in a first direction;
a second chip stacked structure comprising second chips including a second base chip offset-stacked along the first direction and mounted on an upper surface of an uppermost one of the first stacked chips of the first chip stacked structure, and one or more second stacked chips sequentially offset-stacked on the second base chip such that each of the second stacked chips protrudes beyond a side surface of an adjacent lower second chip in the first direction;
a bonding wire electrically connecting the substrate pad to at least one of the first chip stacked structure and the second chip stacked structure; and
a support mounted on the upper surface of the package substrate spaced apart from the first chip stacked structure in the first direction and supporting the second chip stacked structure,
wherein the support supports a portion of a lower surface of the second base chip,
wherein a center of each of the second chips does not vertically overlap the first base chip, and
wherein the second base chip is a lowermost second chip of the second chips.
2 . The semiconductor package of claim 1 , wherein the second stacked chip structure completely overlaps the support in a vertical direction.
3 . The semiconductor package of claim 1 , wherein the support comprises dummy silicon.
4 . The semiconductor package of claim 1 , wherein the support comprises a semiconductor chip.
5 . The semiconductor package of claim 4 , wherein the semiconductor chip comprises a controller chip.
6 . The semiconductor package of claim 4 , wherein the semiconductor chip comprises a frequency boosting interface (FBI).
7 . The semiconductor package of claim 4 , wherein the semiconductor chip comprises a dynamic random access memory (DRAM).
8 . The semiconductor package of claim 1 , wherein the support comprises a first semiconductor chip mounted on an upper surface of the package substrate and a second semiconductor chip stacked on an upper surface of the first semiconductor chip.
9 . The semiconductor package of claim 1 , wherein the support is one of a plurality of supports,
wherein each support of the plurality of supports are spaced apart from each other in the first direction and positioned on the upper surface of the package substrate.
10 . The semiconductor package of claim 9 , wherein each support of the plurality of supports is a semiconductor chip.
11 . The semiconductor package of claim 10 , wherein a first support of the plurality of supports comprises a controller chip and a second support of the plurality of supports comprises a DRAM chip.
12 . A semiconductor package comprising:
a package substrate including a substrate pad;
a first chip stacked structure comprising first chips including a first base chip mounted on an upper surface of the package substrate, and one or more first stacked chips sequentially offset-stacked on the first base chip such that each of the first stacked chips protrudes beyond a side surface of an adjacent lower first chip in a first direction;
a second chip stacked structure comprising second chips including a second base chip offset-stacked along the first direction and mounted on an upper surface of an uppermost one of the first stacked chips of the first chip stacked structure, and one or more second stacked chips sequentially offset-stacked along the first direction on the second base chip such that each of the second stacked chips protrudes beyond a side surface of an adjacent lower second chip in the first direction;
a third chip stacked structure comprising third chips including a third base chip offset-stacked along the first direction and mounted on an upper surface of an uppermost one of the second stacked chips of the second chip stacked structure, and one or more third stacked chips sequentially offset-stacked along the first direction on the third base chip such that each of the third stacked chips protrudes beyond a side surface of an adjacent lower third chip in the first direction;
a bonding wire electrically connecting the substrate pad to at least one of the first chip stacked structure and the second chip stacked structure;
a first support mounted on the upper surface of the package substrate, spaced apart from the first chip stacked structure in the first direction, and supporting the second chip stacked structure; and
a second support spaced apart from the first and second chip stacked structures in the first direction and supporting the third chip stacked structure,
wherein the first support supports the second chip stacked structure by supporting a lower surface of the second base chip,
wherein the second support supports the third chip stacked structure by supporting a lower surface of the third base chip,
wherein a center of each of the second chips does not vertically overlap the first base chip,
wherein a center of each of the third chips does not vertically overlap the second base chip, and
wherein the second base chip is a lowermost one of the second chips and the third base chip is a lowermost one of the third chips.
13 . The semiconductor package of claim 12 , wherein the second support is located on an upper surface of the first support.
14 . The semiconductor package of claim 12 , wherein the second support is spaced apart from the first support in the first direction and is positioned on the upper surface of the package substrate.
15 . The semiconductor package of claim 12 , wherein the first support and the second support each comprise dummy silicon.
16 . The semiconductor package of claim 12 , wherein the first support and the second support each comprise a semiconductor chip.
17 . A semiconductor package comprising:
a package substrate including a substrate pad;
a first chip stacked structure comprising first chips including a first base chip mounted on an upper surface of the package substrate, and one or more first stacked chips sequentially offset-stacked on the first base chip such that each of the first stacked chips protrudes beyond a side surface of an adjacent lower first chip in a first direction;
a second chip stacked structure comprising second chips including a second base chip offset-stacked and mounted on an upper surface of an uppermost one of the first chips of the first chip stacked structure, and one or more second stacked chips sequentially offset-stacked on the second base chip such that each of the second stacked chips protrudes beyond a side surface of an adjacent lower second chip in the first direction;
a third chip stacked structure comprising third chips including a third base chip mounted to be spaced apart from the first base chip in the first direction and on the upper surface of the package substrate, and one or more third stacked chips sequentially offset-stacked on the third base chip such that each of the third stacked chips protrudes beyond a side surface of an adjacent lower third chip in a second direction opposite the first direction;
a fourth chip stacked structure comprising fourth chips including a fourth base chip offset-stacked mounted on an upper surface of an uppermost one of the fourth chips of the fourth chip stacked structure, and one or more fourth stacked chips sequentially offset-stacked on the fourth base chip such that each of the fourth stacked chips protrudes beyond a side surface of an adjacent lower first chip in the second direction; and
a support mounted on the upper surface of the package substrate to be spaced apart from the first chip stacked structure in the first direction and spaced apart from the third chip stacked structure in the second direction and supporting the second chip stacked structure and the fourth chip stacked structure,
wherein the support supports the second chip stacked structure by supporting a lower surface of the second base chip and supports the fourth chip stacked structure by supporting a lower surface of the fourth base chip,
wherein a center of each of the second chips does not vertically overlap the first base chip and a center of each of the fourth chips does not vertically overlap the third base chip, and
wherein the second base chip is a lowermost one of the second chips, and the fourth base chip is a lowermost one of the fourth chips.
18 . The semiconductor package of claim 17 , wherein a vertical distance from the upper surface of the package substrate to the lower surface of the second base chip is equal to a vertical distance from the upper surface of the package substrate to the lower surface of the fourth base chip.
19 . The semiconductor package of claim 17 , wherein the support comprises a semiconductor chip.
20 . The semiconductor package of claim 19 , wherein the semiconductor chip comprises a controller chip.