Guard rings for cascode gallium nitride devices
Implementations of semiconductor devices may include: a plurality of drain fingers and a plurality of source fingers interdigitated with one another; at least one gate; and at gate bus formed to completely surround the plurality of drain fingers and the plurality of source fingers; wherein the gate bus is mechanically and electrically coupled to the at least one gate.
1. A semiconductor device comprising:
a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gate pads;
an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and
a guard ring;
wherein the one or more gate pads of the D-mode transistor couple with the one or more source pads of the E-mode transistor, an electrical ground, and the guard ring.
2. The semiconductor device of claim 1 , wherein the D-mode transistor is a gallium nitride (GaN) high electron mobility transistor (HEMT).
3. The semiconductor device of claim 1 , wherein the E-mode transistor is a silicon (Si) field effect transistor (FET).
4. The semiconductor device of claim 1 , further comprising a gate bus formed as the guard ring.
5. The semiconductor device of claim 1 , wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame.
6. The semiconductor device of claim 1 , further comprising a pin out from each of the drain of the D-mode transistor and a gate and a source of the E-mode transistor.
7. The semiconductor device of claim 1 , wherein a source of the D-mode transistor is coupled to a drain of the E-mode transistor.
8. The semiconductor device of claim 1 , wherein a source of the D-mode transistor and a drain of the E-mode transistor are coupled together through a wire bond.
9. A semiconductor device comprising:
a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gate pads;
an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and
a guard ring;
wherein the one or more gate pads of the D-mode transistor couple with the one or more source pads of the E-mode transistor, an electrical ground, and the guard ring St; and
wherein the source is not grounded.
10. The semiconductor device of claim 9 , wherein the D-mode transistor is a gallium nitride (GaN) high electron mobility transistor (HEMT).
11. The semiconductor device of claim 9 , wherein the E-mode transistor is a silicon (Si) field effect transistor (FET).
12. The semiconductor device of claim 9 , further comprising a gate bus formed as the guard ring.
13. The semiconductor device of claim 9 , wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame.
14. The semiconductor device of claim 9 , further comprising a pin out from each of the drain of the D-mode transistor and a gate and a source of the E-mode transistor.
15. The semiconductor device of claim 9 , wherein of a source of the D-mode transistor is coupled to a drain of the E-mode transistor.
16. The semiconductor device of claim 9 , wherein a source of the D-mode transistor and a drain of the E-mode transistor are coupled together through a wire bond.
17. A semiconductor device comprising:
a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gate pads;
an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and
a second guard ring surrounding an outer perimeter of a first guard ring, the first guard ring coupled with the one or more gate pads of at least the D-mode transistor;
wherein the one or more gate pads of the D-mode transistor couple with the one or more source pads of the E-mode transistor and an electrical ground.
18. The semiconductor device of claim 17 , further comprising a gate bus formed as the first guard ring of the D-mode transistor.
19. The semiconductor device of claim 17 , wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame.