Integrated circuit with a fin and gate structure and method making the same
The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.
1. A semiconductor structure comprising:
a first device fin and a second device fin formed on a substrate;
a first dielectric fin and a second dielectric fin formed on the substrate, wherein the first dielectric fin being interspersed between the first and second device fins, the second dielectric fin is spaced away from the first and second device fins; and
a gate stack formed on the first and second device fins and the first and second dielectric fins, wherein
the first dielectric fin includes a first dielectric material layer and is free of a second dielectric material layer;
the second dielectric fin includes both the first and second dielectric material layers; and
the first and second dielectric material layers are different from each other in composition.
2. The semiconductor structure of claim 1 , wherein
the first dielectric material layer includes a high-k dielectric material; and
the second dielectric material layer includes a carbon-containing material.
3. The semiconductor structure of claim 2 , wherein
the first dielectric material layer is chosen from a metal oxide, a metal nitride and a combination thereof; and
the second dielectric material layer includes carbon and silicon.
4. The semiconductor structure of claim 3 , wherein
the first dielectric material layer includes at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), and aluminum oxide (Al 2 O 3 ); and
the second dielectric material layer includes one of silicon carbon oxide, silicon carbon oxynitride, and silicon carbon nitride.
5. The semiconductor structure of claim 1 , wherein the first dielectric fin includes a first width and the second dielectric fin includes a second width greater than the first width.
6. The semiconductor structure of claim 5 , further comprising:
a third dielectric fin having a third width that is greater than the first width and less than the second width; and
the third dielectric fin includes the first dielectric material layer and is free of the second dielectric material layer.
7. The semiconductor structure of claim 6 , wherein
the first and second device fins are oriented in a first direction;
the gate stack is oriented in a second direction being orthogonal to the first direction;
the first, second and third dielectric fins are oriented in the first direction; and
the dielectric fins further include a fourth dielectric fin oriented in the second direction.
8. The semiconductor structure of claim 7 , wherein
the fourth dielectric fin has a fourth width greater than the second width; and
the fourth dielectric fin includes both the first and second dielectric material layers.
9. The semiconductor structure of claim 1 , wherein the first dielectric material layer surrounds the second dielectric material layer and contacts sidewall surfaces of the second dielectric material layer in the second dielectric fin.
10. A method for fabricating an integrated circuit, comprising:
forming a device fin structure on a substrate, wherein the device fin structure includes a plurality of device fins and defines a first trench and a second trench with different widths;
filling the first and second trenches with a first, a second and a third dielectric material layer sequentially such that the first and second dielectric material layers completely fill the first trench and the first, second and third dielectric material layers completely fill the second trench; and
selectively removing upper portions of the first dielectric material layer, resulting in a first dielectric fin and a second dielectric fin being spaced away from two adjacent devices fins of the device fins, wherein
the first dielectric fin includes the second dielectric material layer and is free of the third dielectric material layer; and
the second and third dielectric material layers are different from each other in composition.
11. The method of claim 10 , further comprising forming a gate stack disposed on the device fins and the dielectric fins.
12. The method of claim 11 , wherein
the filling of the first and second trenches includes performing an atomic layer deposition (ALD) process to deposit the second dielectric material layer in the trenches; and
depositing the third dielectric layer on the second dielectric material layer to fill in the trenches, using one of spin-on coating and flowable chemical vapor deposition (FCVD) such that the second dielectric material layer surrounds the third dielectric material layer and contacts sidewall surfaces of the third dielectric material layer in the second dielectric fin.
13. The method of claim 12 , further comprising a chemical mechanical polishing (CMP) process to recess both the second and third dielectric material layer after the depositing of the third dielectric material layer.
14. The method of claim 12 , wherein
the second dielectric material layer includes a high-k dielectric material; and
the third dielectric material layer includes a carbon-containing material.
15. The method of claim 14 , wherein
the first dielectric material layer includes at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), and aluminum oxide (Al 2 O 3 ); and
the second dielectric material layer includes one of silicon carbon oxide, silicon carbon oxynitride, and silicon carbon nitride.
16. The method of claim 10 , wherein
the first trench has a first width and the second trench has a second width greater than the first width;
the filling of the first and second trenches includes completely filling the first trench with the first and second dielectric material layers such that the first dielectric fin in the first trench is free of the third dielectric material layer; and
the filling of the first and second trenches includes completely filling the second trench with the first, second and third dielectric material layers such that the second dielectric fin in the second trench includes both the second and third dielectric material layers.
17. A semiconductor structure, comprising:
a first device fin and a second device fin formed on a substrate;
a first dielectric fin formed on the substrate and disposed between the first and second device fins;
a second dielectric fin formed on the substrate and disposed on a side of the second device fin opposite to the first device fin; and
gate stacks disposed on the first and second device fins and the first and second dielectric fins, wherein
the first dielectric fin includes a first dielectric material layer and is free of a second dielectric material layer;
the second dielectric fin includes both the first and second dielectric material layers; and
the first and second dielectric material layers are different from each other in composition.
18. The semiconductor structure of 17 , wherein a first portion of the gate stacks is inserted in a first gap between the first device fin and the dielectric fin, and a second portion of the gate stack is inserted in a second gap between the second device fin and the dielectric fin.
19. The semiconductor structure of claim 17 , wherein the second dielectric material layer surrounds the third dielectric material layer and contacts sidewall surfaces of the third dielectric material layer in the second dielectric fin.
20. The semiconductor structure of claim 19 , wherein a top surface of the first dielectric material layer and a top surface of the second dielectric material layer in the second dielectric fin are coplanar.