Integrated circuits and processes for protection of standard cell performance from context effects
Integrated circuit ( 5 ) includes substrate ( 10 ) with surface ( 20 ) and structure ( 30 ) including base levels ( 45. i, 45 .( i +1)), terminating cells ( 48, 49 ), and block ( 40 ) of standard cells arranged in rows ( 42. i, 42 .( i +1)), and another type of block ( 60 ) outside block ( 40 ). Standard cells at at least two edges of block ( 40 ) have the following protections: (1) block ( 60 ) has strip of separation ( 41. j ) having at least a minimum width from the edges of block ( 40 ), and protected by one of the following: (2) terminating cells ( 48, 49 ) reduce context effect and some terminating cells ( 48 ) are placed at at least one end of rows ( 42. i, 42 .( i +1)) of standard cells within first-named block ( 40 ), and ( 3 ) the terminating cells ( 48, 49 ) reduce context effect and some terminating cells ( 49 ) are at one end of a column of standard cells within block ( 40 ). Other structures, devices, and processes are also disclosed.
1. An electronic design process of designing integrated circuits, the process comprising:
dividing cells into classes including a first class of cells susceptible to context effects and a second class of cells that cause context effects in cells sensitive to timing disruption if placed proximate the first class of cells;
placing, in a first place and route region, cells that are included in the first class of cells adjacent other cells in the first class;
removing from the first place and route region any cells from the second class of cells;
placing cells from the second class of cells into a second place and route region nonadjacent to the first place and route region; and
buffering at least some of the second class cells thus placed so that they are buffered for context effects reduction from the cells of the first class, wherein the buffering includes providing a cell-block separation strip having a minimum width of at least eight track widths.
2. The process of claim 1 , including storing a representation of the design rules and the placement of cells in an automatically readable form with a first physical medium, and electronically executing the placing and buffering steps to generate and store a pattern representing an integrated circuit layout to a second physical medium.
3. The electronic design process of claim 1 , wherein the storing includes storing a third class of cells that do not cause timing disruption and are insensitive to timing disruption, and wherein the buffering includes placing at least one cell from the third class of cells adjacent to at least one of the second-class cells to buffer the second-class cell from a first-class cell.
4. The process of claim 3 , wherein the third class cells include row buffer cells selected from a group consisting of: 1) filler, 2) filler tap, 3) end-tap, and 4) decoupling capacitor.
5. The process of claim 3 wherein the third class cells include column buffer cells including decoupling capacitor and also includes a tap cell situated directly above or below a row buffer tap cell.
6. The process of claim 1 , wherein the buffering includes providing a set of filler cells adjacent to at least one of the first-class cells and with the cell block separation strip along the set of filler cells and separating the set of filler cells from at least one of the cells from the second class of cells.
7. The process of claim 1 , wherein the buffering includes providing a set of filler cells adjacent to a first selection of the first-class cells and with the cell-block separation strip along the set of filler cells and separating the set of filler cells from at least one other selection of first class cells that is offset from alignment with the first selection of first-class cells.
8. The process of claim 7 , wherein the buffering includes providing a second set of filler cells adjacent to said at least one other selection of first-class cells and with the cell-block separation strip along said second set of filler cells and separating the second set of filler cells from the first set of filler cells.
9. The process of claim 1 , wherein the cells in the second class include at least one level shifter cell, switch cell, electrostatic discharge (ESD) diode, and thick gate dielectric decoupling capacitor cell.
10. The process of claim 1 , wherein the cells in the first class are restricted to cells containing working transistors that produce a logic state output, switch cells, and non-working cells that can potentially be connected to produce a logic state output.
11. A process of manufacturing integrated circuits, the process comprising:
fabricating first sets of cells from a first class of standard cells onto a semiconductor substrate to realize at least part of the circuitry for an integrated circuit;
fabricating, concurrently with fabrication of the first sets of cells, second sets of cells from a second class of cells into regions nonadjacent to the first sets of cells on the substrate; and
fabricating, concurrently with fabrication of the first and second sets of cells, buffering structures having a minimum width of at least eight track widths that reduce context effects in at least some of the first sets of cells from the cells of the second class.
12. The process of claim 11 , wherein a first group of cells in the first class are placed adjacent a second group of cells in the first class.
13. The process of claim 11 , wherein the buffering structures do not cause timing disruption to an adjacent cell and are insensitive to timing disruption from such adjacent cell.
14. The process of claim 11 , wherein the fabricating of buffering structures situates at least one buffer cell adjacent to at least one of the first-class cells to buffer the first-class cell from a second-class cell.