Granted Patent B2

US 12,310,117 · App. 17/498,330 · Granted May 20, 2025

Inventors: Kwan Yeob Chae (Seoul, KR); San Kang (Hwaseong-si, KR)

Assignee: SAMSUNG ELECTRONICS CO., LTD.

H10D89/611H03K19/0185H03K19/17744

Abstract

Claims (50)

1. A semiconductor device, comprising:

a first wiring that receives an input signal and extends in a first direction;

a first gate wiring that extends in a second direction that intersects the first direction;

a first impurity region disposed in a first active region on one side of the first gate wiring and is connected to the first wiring;

a second impurity region disposed in the first active region on an other side of the first gate wiring and is connected to the first wiring, wherein the second impurity region is spaced apart from the first impurity region in the first direction;

a second gate wiring that extends in the second direction and spaced apart from the first gate wiring in the first direction, and connected to the first wiring;

a first inverter that includes the second gate wiring and is connected to the first wiring through which the first inverter receives the input signal;

a second wiring that extends in the second direction, is disposed higher than the first wiring, and is connected to the first wiring; and

a third wiring that extends in the first direction, is disposed lower than the second wiring, and is connected to the second wiring,

wherein the first and second impurity regions are connected to the third wiring.

2. The semiconductor device of claim 1 , wherein the first gate wiring is connected to the first wiring.

3. The semiconductor device of claim 2 , further comprising:

a fourth wiring connected to a power supply voltage and that extends in the first direction;

a third impurity region disposed on one side of the first gate wiring, is spaced apart from the first impurity region in the second direction, and is connected to the fourth wiring; and

a fourth impurity region disposed on an other side of the first gate wiring, is spaced apart from the second impurity region in the second direction, and is connected to the fourth wiring.

4. The semiconductor device of claim 1 , further comprising:

a plurality of third gate wirings that extend in the second direction, and are spaced apart from the second gate wiring in the first direction;

a second inverter that includes the plurality of third gate wirings;

a fifth wiring that transmits an output of the first inverter to the second inverter; and

a sixth wiring that transmits an output of the second inverter to an output terminal,

wherein a width in the second direction of the sixth wiring is greater than a width in the second direction of the fifth wiring.

5. The semiconductor device of claim 4 , wherein the fifth wiring and the sixth wiring are disposed higher than the plurality of third gate wirings.

6. A semiconductor device, comprising:

a first wiring that receives an input signal and extends in a first direction;

a first gate wiring that extends in a second direction that intersects the first direction;

a first impurity region disposed in a first active region on one side of the first gate wiring and is connected to the first wiring;

a second impurity region disposed in the first active region on an other side of the first gate wiring and connected to the first wiring, wherein the second impurity region is spaced apart from the first impurity region in the first direction;

a fourth wiring that receives a power supply voltage and extends in the first direction;

a third impurity region disposed in a second active region on one side of the first gate wiring and is spaced apart from the first impurity region in the second direction;

a fourth impurity region disposed in the second active region on an other side of the first gate wiring and is spaced apart from the second impurity region in the second direction and from the third impurity region in the first direction; and

an inverter connected to the first wiring through which the inverter receives the input signal;

a buffer connected to the first wiring;

a second wiring that extends in the second direction, is disposed higher than the first wiring, and is connected to the first wiring, and

a third wiring that extends in the first direction, is disposed lower than the second wiring, and is connected to the second wiring,

wherein the first and second impurity regions are connected to the third wiring, and

the first gate wiring is connected to the first wiring.

7. The semiconductor device of claim 6 , wherein the third and fourth impurity regions are connected to the fourth wiring.

8. A semiconductor device, comprising:

a diode buffer cell that includes a substrate on which an active region is defined; and

a tap cell that is spaced apart from the diode buffer cell and grounds the substrate,

wherein the diode buffer cell comprises:

a first wiring that is disposed on the active region, receives an input signal, and extends in a first direction;

a first gate wiring that is disposed on the active region and extends in a second direction that intersects the first direction;

a first impurity region that is disposed in the active region on one side of the first gate wiring, and is connected to the first wiring;

a second impurity region that is disposed in the active region on an other side of the first gate wiring, and is connected to the first wiring;

a buffer connected to the first wiring;

a second wiring that extends in the second direction, is disposed higher than the first wiring, and is connected to the first wiring, and

a third wiring that extends in the first direction, is disposed lower than the second wiring, and is connected to the second wiring,

wherein the first and second impurity regions are connected to the third wiring, and

the first gate wiring is connected to the first wiring.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (130)