Non-volatile memory with fast partial page operation
A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.
1. An apparatus, comprising:
a plurality of non-volatile memory cells including a plurality of partial planes, each of the partial planes corresponding to a non-overlapping subset of the memory cells connected along a word line; and
one or more control circuits connected to the non-volatile memory cells, the one or more control circuits are configured to read data from and write data to a selected one of the partial planes by applying to the word line one or more voltages that are dependent on a resistive/capacitive behavior of the word line in the partial plane.
2. The apparatus of claim 1 , wherein each of the partial planes corresponds to a contiguous subset of the plurality of memory cells.
3. The apparatus of claim 1 , wherein each of the partial planes corresponds to a plurality of contiguous subsets of the plurality of memory cells having a similar resistive/capacitive behavior.
4. The apparatus of claim 1 , wherein the one or more control circuits are configured to write data to the selected one of the partial planes by applying one of a plurality of program voltage pulse levels to the word line, an amplitude of a voltage pulse applied to the word line when writing data to the selected one of the partial planes is dependent on the resistive/capacitive behavior of the selected one of the partial planes.
5. The apparatus of claim 4 , wherein the one or more control circuits are configured to store data in the memory cells in a binary format and write data to the selected one of the partial planes by applying a single voltage pulse to the word line.
6. The apparatus of claim 4 , wherein the one or more control circuits are configured to write data to the selected one of the partial planes by applying one or more voltage pulses to a first end of the word line, the one or more voltage pulses having a larger amplitude for a partial plane further from the first end than for a partial plane nearer the first end.
7. The apparatus of claim 1 , wherein the one or more control circuits are configured to read data from the selected one of the partial planes by applying one of a plurality of sensing waveforms to the word line, an amplitude of a sensing waveform applied to the word line when writing data to the selected one of the partial planes is dependent on the resistive/capacitive behavior of the selected one of the partial planes.
8. The apparatus of claim 7 , wherein the one or more control circuits are configured to read data from the selected one of the partial planes by applying the sensing waveform to a first end of the word line, the sensing waveform having a larger amplitude for a partial plane further from the first end than for a partial plane nearer the first end.
9. The apparatus of claim 1 , wherein the control circuit is configured to receive a partial page of data, break the partial page of data into a plurality of chunks of data, scramble the chunks of data, and write the scrambled plurality of chunks of data to the selected one of the partial planes.
10. The apparatus of claim 1 , wherein the non-volatile memory cells comprises a three-dimensional semiconductor memory device in which the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.
11. A method, comprising:
receiving a command to access a partial page of data in a contiguous subset of memory cells connected to a word line;
determining a voltage to apply to the word line based on a location of the contiguous subset of memory cells along the word line relative to a word line driver; and
accessing the partial page of data, the accessing including applying the determined voltage to the word line.
12. The method of claim 11 , wherein the command to access the partial page of data is a program command to write the partial page of data to the contiguous subset of memory cells, and the voltage applied to the word line is a programming pulse having an amplitude dependent upon the location of the contiguous subset of memory cells along the word line.
13. The method of claim 12 , wherein the program command is to write the partial page of data in a binary format to the contiguous subset of memory cells by applying a single voltage pulse to the word line.
14. The method of claim 12 , further comprising:
receiving the partial page of data;
breaking the partial page of data into a plurality of chunks of data; and
scrambling the chunks of data, wherein accessing the partial page of data includes writing the scrambled plurality of chunks of data to the contiguous subset of memory cells.
15. The method of claim 11 , wherein the command to access the partial page of data is a read command to read the partial page of data from the contiguous subset of memory cells, and the voltage applied to the word line is a sensing voltage having an amplitude dependent upon the location of the contiguous subset of memory cells along the word line.
16. A system, comprising:
a non-volatile memory controller; and
a memory die, comprising:
an array of non-volatile memory cells; and
an on-die control circuit connected to the array of non-volatile memory cells, the control circuit is configured to read and write data as a full page, a full page corresponding to a plurality of memory cells connected along a word line, the control circuit is further configured to read and write data as one of a plurality of partial pages, each of the partial pages corresponding to a contiguous subset of the plurality of memory cells connected to the word line, wherein one or more voltages applied to the word line in a read or write operation of a selected partial page are based on a capacitive behavior of a portion of word line along which the memory cells of the selected partial page are connected.
17. The system of claim 16 , wherein the on-die control circuit is configured to write data to the selected one of the partial pages by applying one of a plurality of program voltage pulse levels to the word line, an amplitude of a voltage pulse applied to the word line when writing data to the selected partial page is dependent on the capacitive behavior of the selected one of the partial pages.
18. The system of claim 17 , wherein the on-die control circuit is configured to store data in the memory cells in a binary format and write data to the selected partial page by applying a single voltage pulse to the word line.
19. The system of claim 16 , wherein the on-die control circuit is configured to write data to the selected partial page by applying one or more voltage pulses to a first end of the word line, the one or more voltage pulses having a larger amplitude for a partial plane further from the first end than for a partial plane nearer the first end.
20. The system of claim 16 , wherein the on-die control circuit is configured to read data from the selected partial page by applying one of a plurality of sensing waveforms to the word line, an amplitude of a sensing waveform applied to the word line when reading data from the selected one of the partial pages is dependent on the capacitive behavior of the selected one of the partial pages.