IP Library › Granted Patent US 11,069,771
Granted Patent B2
US 11,069,771 · App. 16/613,549 · Granted Jul 20, 2021

Semiconductor device

Inventors: Minoru Nakagawa (Kyoto, JP); Yuki Nakano (Kyoto, JP); Masatoshi Aketa (Kyoto, JP); Masaya Ueno (Kyoto, JP); Seigo Mori (Kyoto, JP); Kenji Yamamoto (Kyoto, JP)
Assignee: ROHM CO., LTD.
H01L29/0619H01L29/0657H01L29/0692H01L29/1095H01L29/42376H01L29/1608H01L29/404
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,069,771
App. No.
16/613,549
Granted
Jul 20, 2021
Kind
B2
Abstract

A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.0, a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench, a source region of the first conductivity type formed in a surface layer portion of the body region, and a drain electrode connected to the second main surface of the semiconductor layer.

Claims (31)

1. A semiconductor device comprising:

a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side;

a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer;

a trench source structure including a source trench formed deeper than the gate trench and formed across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.0;

a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench;

a source region of the first conductivity type formed in a surface layer portion of the body region; and

a drain electrode connected to the second main surface of the semiconductor layer;

wherein an aspect ratio of the trench source structure is greater than an aspect ratio of the trench gate structure.

2. The semiconductor device according to claim 1 , wherein an aspect ratio of the trench source structure is not less than 0.5 and not more than 18.0.

3. The semiconductor device according to claim 1 , wherein a depletion layer spreads further from a boundary region between the semiconductor layer and the well region toward a region of a second main surface side than from a bottom wall of the gate trench in the semiconductor layer toward a region of the second main surface side.

4. The semiconductor device according to claim 3 , wherein the depletion layer overlaps to the bottom wall of the gate trench.

5. The semiconductor device according to claim 1 , wherein the well region is formed in a region of the semiconductor layer along a side wall of the source trench.

6. The semiconductor device according to claim 1 , wherein the well region is formed in a region of the semiconductor layer along a bottom wall of the source trench.

7. The semiconductor device according to claim 1 , wherein the well region is formed continuously in a region of the semiconductor layer along a side wall, a bottom wall, and a corner portion connecting the side wall and the bottom wall of the source trench.

8. The semiconductor device according to claim 1 , wherein the well region is connected to the body region.

9. The semiconductor device according to claim 1 , wherein the trench source structure includes a barrier forming layer interposed in a region between the source trench and the source electrode and having a higher potential barrier than a potential barrier between the well region and the source electrode.

10. The semiconductor device according to claim 9 , wherein the barrier forming layer includes an insulating barrier forming layer made of an insulating material.

11. The semiconductor device according to claim 9 , wherein the barrier forming layer includes a conductive barrier forming layer made of a conductive material differing from a conductive material of the source electrode.

12. The semiconductor device according to claim 9 , wherein the barrier forming layer includes an insulating barrier forming layer made of an insulating material, and a conductive barrier forming layer made of a conductive material differing from a conductive material of the source electrode.

13. The semiconductor device according to claim 9 , wherein the barrier forming layer is formed along a side wall, a bottom wall, and a corner portion connecting the side wall and the bottom wall of the source trench.

14. The semiconductor device according to claim 1 , further comprising: a contact region of the second conductivity type formed in a region of the semiconductor layer along a side wall of the source trench and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the body region.

15. The semiconductor device according to claim 1 , further comprising: a contact region of the second conductivity type formed in a region of the semiconductor layer along a bottom wall of the source trench and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the body region.

16. A semiconductor device comprising:

a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side;

a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer;

a trench source structure including a source trench formed deeper than the gate trench and formed across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.0;

a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench;

a source region of the first conductivity type formed in a surface layer portion of the body region; and

a drain electrode connected to the second main surface of the semiconductor layer; and

wherein the trench source structure includes a barrier forming layer interposed in a region between the source trench and the source electrode and having a higher potential barrier than a potential barrier between the well region and the source electrode, and

the barrier forming layer includes an insulating barrier forming layer made of an insulating material, and a conductive barrier forming layer made of a conductive material differing from a conductive material of the source electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2019
From: NAKAGAWA, MINORU; NAKANO, YUKI; AKETA, MASATOSHI; UENO, MASAYA; MORI, SEIGO; YAMAMOTO, KENJI
To: ROHM CO., LTD.
Reel/Frame 051012/0112 →
Priority Claims (4)
JP JP2017-098423 · May 17, 2017 · national
JP JP2018-042133 · Mar 8, 2018 · national
JP JP2018-094956 · May 16, 2018 · national
JP JP2018-094957 · May 16, 2018 · national
Continuity (1)
Related Publication 20200243641A1 · Jul 30, 2020
Cited By (4)
US 12,249,634 US 12,324,203 US 12,477,773 US 12,684,860