Suppression of program disturb with bit line and select gate voltage regulation
Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, a method for suppression of program disturb in a flash memory array is provided. The flash memory array comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). During a program memory operation, a first voltage, of a selected SG line, and a second voltage, of an unselected BL, are regulated independently of a power supply voltage of the flash memory array, where the first voltage is regulated in a first range of 0.9V to 1.1V and the second voltage is regulated in a second range of 0.4V to 1.2V.
1. A semiconductor apparatus, comprising:
a processing device; and
a non-volatile memory (NVM) device coupled to the processing device, including:
a memory array comprising NVM cells arranged in rows and columns, wherein each source line of a plurality of source lines and each select-gate (SG) line of a plurality of SG lines respectively couple at least two NVM cells of a same row, and wherein each bit line of a plurality of bit lines couples at least two NVM cells of a same column; and
control circuitry operable to regulate, independently of a power supply voltage, a first voltage of a selected SG line and a second voltage of an unselected bit line, wherein the second voltage is operated to be higher than the power supply voltage, and wherein the control circuitry is further operable to adjust at least one of the first and second voltages responding to a sensing signal.
2. The semiconductor apparatus of claim 1 , wherein a first NVM cell is coupled to the selected SG line during a program operation of the first NVM cell, and a second NVM cell is coupled to the unselected bit line during the program operation, the second NVM cell being adjacent to the first NVM cell in the same row of the NVM array.
3. The semiconductor apparatus of claim 2 , wherein during the program operation, the control circuitry is configured to regulate the first voltage in an approximate range of 0.9V to 1.1V.
4. The semiconductor apparatus of claim 2 , wherein during the program operation, the control circuitry is configured to regulate the second voltage in an approximate range of 0.4V to 1.2V.
5. The semiconductor apparatus of claim 1 , wherein the control circuitry is configured to operate the first voltage lower than the power supply voltage.
6. The semiconductor apparatus of claim 1 , wherein the sensing signal is corresponding to a measure of an operating temperature of the NVM device.
7. The semiconductor apparatus of claim 1 , wherein the control circuitry is configured with trim values for the first voltage and the second voltage at the time of manufacture, and wherein the trim values are configured for each block of NVM cells in the NVM device.
8. The semiconductor apparatus of claim 1 , wherein the NVM cells of the memory array are split-gate memory cells manufactured as 40 nm nodes.
9. The semiconductor apparatus of claim 1 , wherein the NVM cells of the memory array are two-transistor (2T) memory cells manufactured as 40 nm nodes.
10. The semiconductor apparatus of claim 1 , wherein the processing device and the NVM device are disposed on a same semiconductor substrate.
11. An integrated circuit comprising:
a flash memory device comprising:
a memory array including rows and columns of memory cells, wherein memory cells of two adjacent rows share a same source line, memory cells of a same row are coupled to a same select-gate (SG) line, and memory cells of a same column are coupled to a same bit line; and
a control circuit configured at least to:
regulate, independently of a power supply voltage, both a first voltage of a selected SG line and a second voltage of an unselected bit line, wherein, during a program operation of a first memory cell, the control circuit is configured to regulate the first voltage in a first range of 0.9V to 1.1V and the second voltage in a second range of 0.4V to 1.2V; and
adjust at least one of the first voltage and the second voltage responding to a sensing signal.
12. The integrated circuit of claim 11 , wherein during the program operation, the first memory cell is coupled to the selected SG line and a second memory cell is coupled to the unselected bit line, the second memory cell being adjacent to the first memory cell in the same row of the memory array.
13. The integrated circuit of claim 11 , wherein the control circuit is configured to operate the first voltage lower than the power supply voltage.
14. The integrated circuit of claim 11 , wherein the control circuit is configured to operate the second voltage higher than the power supply voltage.
15. The integrated circuit of claim 11 , wherein the control circuit is configured to sense an operating temperature of the flash memory device.
16. The integrated circuit of claim 11 , wherein the sensing signal is based on a measure of an operating temperature of the flash memory device.
17. The integrated circuit of claim 11 , wherein the control circuit is configured with trim values for the first voltage and the second voltage at the time of manufacture, and the trim values are configured for each block of memory cells in the flash memory device.
18. The integrated circuit of claim 11 , wherein the memory cells of the flash memory device are split-gate memory cells manufactured as 40 nm nodes.
19. The integrated circuit of claim 11 , wherein the memory cells of the flash memory device are two-transistor (2T) memory cells manufactured as 40 nm nodes.
20. The integrated circuit of claim 11 , wherein the flash memory device is configured to be connected to a microprocessor.