Non-volatile memory with erase verify skip
A non-volatile storage apparatus is configured to perform erase verify during an erase process in order to account for differences in erase speed. In order to reduce the time used to perform the erase process (which includes the erase verify), the erase verify operation is skipped for certain memory cells based on a system parameter. For example, when erasing a block of memory cells, a series of erase voltage pulses are applied to the NAND strings in outer sub-blocks and inner sub-blocks of the block. Erase verify is performed between erase voltage pulses for NAND strings in the outer sub-blocks while skipping erase verify for NAND strings in the inner sub-blocks. Performing erase verify between erase voltage pulses for NAND strings in the inner sub-blocks is started at a predetermined number of erase voltage pulses after the NAND strings in the outer sub-blocks successfully erase verify.
1. A non-volatile storage apparatus, comprising:
a non-volatile memory structure including multiple groups of memory cells, each group includes a plurality of connected memory cells, all of the groups are connected to a common bit line and a common word line, a subset of the groups serve as one or more reference groups, groups of the multiple groups that are not one of the one or more reference group are non-reference groups; and
a control circuit connected to the non-volatile memory structure, the control circuit is configured to:
apply doses of an erase signal to the groups,
perform erase verify between doses of the erase signal for the one or more reference groups until the one or more reference groups successfully erase verify while skipping erase verify between doses of the erase signal for the non-reference groups, and
for each of the non-reference groups, start to perform erase verify between doses of the erase signal at a respective predetermined number of doses of the erase signal after the one or more reference groups successfully erase verify and continue to perform erase verify for the respective non-reference group between doses of the erase signal until the respective non-reference group successfully erase verifies.
2. The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to apply the doses of the erase signal to the groups by applying a series of bursts of voltage such that each burst of voltage is higher in magnitude than an immediately previous burst of voltage;
the bursts of voltage increase by a first step size prior to the one or more reference groups successfully erase verify;
the bursts of voltage increase by a second step size for a burst of the erase signal immediately after the one or more reference groups successfully erase verify, the second step size is larger than the first step size; and
the bursts of voltage increase by the first step size subsequent to the burst of the erase signal immediately after one or more reference groups successfully erase verify.
3. The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to inhibit the one or more reference groups from erasing, while applying doses of the erase signal to the non-reference groups, after the one or more reference groups successfully erase verify.
4. The non-volatile storage apparatus of claim 1 , wherein:
the non-reference groups comprise groups that are positioned at an interior portion of the memory structure displaced from edges of the of memory structure; and
the one or more reference groups comprise one or more groups positioned at one or more outer portions of the memory structure between the interior portion of the memory structure and at least one of the edges of the memory structure.
5. The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to store the respective predetermined number of doses prior to applying the doses of the erase signal to the groups.
6. The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to skip erase verify for the one or more reference groups between doses of the erase signal for which the control circuit is configured to perform erase verify for the non-reference groups.
7. The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to cause the one or more reference groups and the non-reference groups to experience erase prior to the one or more reference groups successfully erase verifying.
8. The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to apply the doses of the erase signal to the groups by applying voltage pulses to the common bit line that increase in magnitude from pulse to pulse.
9. The non-volatile storage apparatus of claim 1 , wherein:
the non-volatile memory structure is a three dimensional memory structure; and
the groups of memory cells are vertical NAND strings.
10. The non-volatile storage apparatus of claim 9 , wherein:
the three dimensional memory structure is positioned on a memory die; and
the control circuit includes a processing circuit on the memory die.
11. The non-volatile storage apparatus of claim 9 , wherein:
the three dimensional memory structure is positioned on a memory die; and
the control circuit includes a controller separate from the memory die.
12. The non-volatile storage apparatus of claim 9 , wherein:
the three dimensional memory structure is divided into blocks of memory cells;
each of the blocks of memory cells are divided into sub-blocks; and
the vertical NAND strings are in different sub-blocks of a same block.
13. The non-volatile storage apparatus of claim 9 , wherein:
the vertical NAND strings have select transistors;
the control circuit is configured to apply the doses of the erase signal to the groups by generating gate induced drain leakage (GIDL) current to charge up channels of the vertical NAND string; and
the control circuit is configured to generate GIDL current by causing drain-to-gate voltages at the select transistors.
14. The non-volatile storage apparatus of claim 1 , wherein:
the control circuit is configured to apply the doses of the erase signal to the groups by applying a series of bursts of voltage such that each burst of voltage is higher in magnitude than an immediately previous burst of voltage;
the bursts of voltage increase by a first step size prior to the one or more reference groups successfully erase verify;
the bursts of voltage increase by a second step size for a burst of the erase signal immediately after one or more reference groups successfully erase verify, the second step size is larger than the first step size;
the bursts of voltage increase by the first step size subsequent to the burst of the erase signal immediately after one or more reference groups successfully erase verify;
the control circuit is configured to inhibit the one or more reference groups from erasing, while applying doses of the erase signal to the groups, after the one or more reference groups successfully erase verify;
the non-reference groups comprise groups are positioned at an interior portion of the memory structure displaced from edges of the of memory structure;
the one or more reference groups comprise one or more groups positioned at one or more outer portions of the memory structure between the interior portion of the memory structure and at least one of the edges of the memory structure and
the control circuit is configured to store the respective predetermined number of doses prior to applying the doses of the erase signal to the groups.