IP Library Granted Patent US 11,087,971
Granted Patent B2
US 11,087,971 · App. 16/685,577 · Granted Aug 10, 2021

Method for manufacturing semiconductor device and manufacturing method of the same

Inventors: Yung-Lung Lin (Taichung, TW); Hau-Yi Hsiao (Chiayi, TW); Chih-Hui Huang (Tainan County, TW); Kuo-Hwa Tzeng (Taipei, TW); Cheng-Hsien Chou (Tainan, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
H01L21/02035H01L21/02052H01L21/02532H01L21/30625H01L21/76251
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Quick Facts
Patent No.
US 11,087,971
App. No.
16/685,577
Granted
Aug 10, 2021
Kind
B2
Abstract

The present disclosure provides a method for wafer bonding, including providing a wafer, forming a sacrificial layer on a top surface of the first wafer, trimming an edge of the first wafer to obtain a first wafer area, cleaning the top surface of the first wafer, removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer having a second wafer area greater than the first wafer area.

Claims (39)

1. A method for wafer bonding, comprising:

providing a first wafer;

forming an epitaxial layer on a top surface of the first wafer;

forming a sacrificial layer over the epitaxial layer subsequent to forming the epitaxial layer;

trimming an edge of the first wafer;

removing the sacrificial layer; and

bonding the top surface of the first wafer to a second wafer subsequent to trimming the edge of the first wafer.

2. The method of claim 1 , wherein:

the first wafer has a first wafer area after trimming the edge of the first wafer;

the second wafer has a second wafer area, wherein the second wafer area is greater than the first wafer area.

3. The method of claim 1 , further comprising cleaning the top surface of the first wafer.

4. The method of claim 3 , wherein cleaning the top surface of the first wafer comprises applying a basic and an acidic chemical to the top surface.

5. The method of claim 1 , wherein a width of a trimmed edge of the first wafer is in a range of from about 1 mm to about 3 mm.

6. The method of claim 1 , wherein a depth of a trimmed edge of the first wafer is in a range of from about 0.01 μm to about 200 μm.

7. The method of claim 1 , wherein the epitaxial layer comprises SiGe.

8. The method of claim 1 , further comprising forming a bonding layer over the second wafer prior to bonding the first wafer to the second wafer.

9. The method of claim 1 , further comprising forming an oxide layer over the top surface of the first wafer subsequent to removing the sacrificial layer.

10. A method for wafer bonding, comprising:

providing a first wafer;

forming a sacrificial layer on a top surface of the first wafer;

forming an epitaxial layer over the top surface of the first wafer subsequent to forming the sacrificial layer;

trimming an edge of the first wafer;

cleaning the top surface of the first wafer;

removing the sacrificial layer; and

bonding the top surface of the first wafer to a second wafer subsequent to trimming the edge of the first wafer.

11. The method of claim 10 , wherein the epitaxial layer comprises SiGe.

12. The method of claim 10 , further comprising forming an oxide layer over the top surface of the wafer subsequent to removing the sacrificial layer.

13. The method of claim 10 , wherein the edge-trimming comprises reducing a diameter of the first wafer in a range of from about 2 mm to about 6 mm in proximal to the first bonding surface.

14. The method of claim 10 , wherein the edge-trimming comprises reducing a thickness of the first wafer in a range of from about 0.01 μm to about 200 μm in proximal to the first bonding surface.

15. The method of claim 10 , further comprising bonding the first wafer having a first area at a first bonding surface to a second wafer having a second area at a second bonding surface, the second area being greater than the first area.

16. A method for forming an edge-trimmed wafer, comprising:

providing a first wafer having a top surface;

forming an epitaxial layer over the top surface of the first wafer;

edge-trimming the first wafer at the top surface subsequent to forming the epitaxial layer; and

reducing a thickness of the epitaxial layer from a first thickness to a second thickness less than the first thickness, wherein the thickness of the epitaxial layer is reduced by performing a planarization operation from the top surface.

17. The method of claim 16 , bonding the top surface of the first wafer to a second wafer, wherein the second wafer has a bonding surface greater than the top surface of the first wafer.

18. The method of claim 16 , further comprising cleaning the top surface by a basic and an acidic etch prior to performing the planarization operation.

19. The method of claim 16 , further comprising ashing and hydrogen fluoride etching after performing the planarization operation.

20. The method of claim 17 , wherein the first wafer is bonded to the second wafer subsequent to edge-trimming the first wafer.

Continuity (2)
Continuation 15922296 · Mar 15, 2018
Related Publication 20200083036A1 · Mar 12, 2020
Cited By (1)
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