Method for wafer bonding including edge trimming
The present disclosure for wafer bonding, including forming an epitaxial layer on a top surface of a first wafer, forming a sacrificial layer over the epitaxial layer, trimming an edge of the first wafer, removing the sacrificial layer, forming an oxide layer over the top surface of the first wafer subsequent to removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer.
1. A method for wafer bonding, comprising:
forming an epitaxial layer on a top surface of a first wafer;
forming a sacrificial layer over the epitaxial layer;
trimming an edge of the first wafer prior to bonding the first wafer to a second wafer;
removing the sacrificial layer;
forming an oxide layer over the top surface of the first wafer subsequent to removing the sacrificial layer; and
bonding the top surface of the first wafer to the second wafer.
2. The method of claim 1 , wherein:
the first wafer has a first wafer area after trimming the edge of the first wafer; and
the second wafer has a second wafer area, wherein the second wafer area is greater than the first wafer area.
3. The method of claim 1 , wherein the top surface of the first wafer is bonded to the second wafer after the oxide layer is formed over the top surface of the first wafer.
4. The method of claim 1 , further comprising cleaning the top surface of the first wafer.
5. The method of claim 4 , wherein cleaning the top surface of the first wafer comprises applying a basic and an acidic chemical to the top surface.
6. The method of claim 4 , wherein the top surface of the first wafer is cleaned after trimming the edge of the first wafer.
7. The method of claim 1 , wherein a width of a trimmed edge of the first wafer is in a range of from about 1 mm to about 3 mm.
8. The method of claim 1 , wherein a depth of a trimmed edge of the first wafer is in a range of from about 0.01 μm to about 200 μm.
9. The method of claim 1 , wherein the epitaxial layer comprises SiGe.
10. A method for wafer bonding, comprising:
forming a sacrificial layer on a top surface of a first wafer;
trimming an edge of the first wafer prior to bonding the first wafer to a second wafer;
removing the sacrificial layer;
forming an epitaxial layer over the top surface of the first wafer subsequent to removing the sacrificial layer;
forming an oxide layer over the epitaxial layer; and
bonding the top surface of the first wafer to the second wafer.
11. The method of claim 10 , wherein the epitaxial layer comprises SiGe.
12. The method of claim 10 , wherein a width of a trimmed edge of the first wafer is in a range of from about 1 mm to about 3 mm.
13. The method of claim 10 , wherein a depth of a trimmed edge of the first wafer is in a range of from about 0.01 μm to about 200 μm.
14. The method of claim 10 , further comprising cleaning the top surface of the first wafer after trimming the edge of the first wafer.
15. The method of claim 14 , wherein cleaning the top surface of the first wafer comprises applying a basic and an acidic chemical to the top surface.
16. A method for forming an edge-trimmed wafer, comprising:
edge-trimming an edge of a top surface of a first wafer prior to bonding the first wafer to a second wafer;
performing chemical mechanical polishing (CMP) on the top surface of the first wafer after edge-trimming the edge of the top surface of the first wafer;
forming an epitaxial layer over the top surface of the first wafer after edge-trimming the edge of the top surface of the first wafer and CMP over the top surface of the first wafer; and
bonding the top surface of the first wafer to the second wafer.
17. The method of claim 16 , further comprising forming an oxide layer over the epitaxial layer.
18. The method of claim 16 , further comprising forming an oxide layer over the top surface of the first wafer subsequent to performing CMP on the top surface of the first wafer.
19. The method of claim 16 , wherein a width of a trimmed edge of the first wafer is in a range of from about 1 mm to about 3 mm.
20. The method of claim 16 , wherein a depth of a trimmed edge of the first wafer is in a range of from about 0.01 μm to about 200 μm.