IP Library › Granted Patent US 11,121,089
Granted Patent B2
US 11,121,089 · App. 16/458,960 · Granted Sep 14, 2021

Integrated circuit package and method

Inventors: Jen-Jui Yu (Taipei, TW); Hao-Jan Pei (Hsinchu, TW); Wei-Yu Chen (Taipei, TW); Chia-Lun Chang (Tainan, TW); Hsiu-Jen Lin (Zhubei, TW); Ching-Hua Hsieh (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L23/5389H01L21/486H01L21/4853H01L21/4857H01L21/563H01L21/565H01L23/3128H01L23/5383H01L23/5386H01L24/19H01L24/24H01L24/97H01L25/16H01L25/50H01L25/0655H01L25/0657H01L25/105H01L2224/24225H01L2224/24265H01L2225/0651H01L2225/06548H01L2225/06568H01L2225/06586H01L2225/1035H01L2225/1058H01L2924/19102
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Quick Facts
Patent No.
US 11,121,089
App. No.
16/458,960
Granted
Sep 14, 2021
Kind
B2
Abstract

In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure being electrically connect to the integrated circuit die, the redistribution structure including a pad; a passive device including a conductive connector physically and electrically connected to the pad; and a protective structure disposed between the passive device and the redistribution structure, the protective structure surrounding the conductive connector, the protective structure including an epoxy flux, the protective structure having a void disposed therein.

Claims (52)

1. A method comprising:

encapsulating an integrated circuit die with an encapsulant;

forming a redistribution structure on the encapsulant, the redistribution structure being electrically connected to the integrated circuit die, the redistribution structure comprising a first pad and a second pad;

dispensing an epoxy flux on the first pad to form a protective structure;

prior to curing the epoxy flux, pressing a passive device into the protective structure to physically couple the passive device to the first pad;

after physically coupling the passive device to the first pad, forming a first conductive connector on the second pad; and

performing a single thermal process to simultaneously cure the protective structure and reflow the first conductive connector, the first conductive connector physically and electrically coupling the passive device to the first pad after the single thermal process.

2. The method of claim 1 further comprising:

placing the integrated circuit die adjacent to a conductive via, the redistribution structure being electrically connected to the conductive via; and

encapsulating the conductive via with the encapsulant.

3. The method of claim 1 , wherein the passive device comprises a second conductive connector, the passive device being pressed into the protective structure until the second conductive connector contacts the first pad, the second conductive connector comprising a reflowable material.

4. The method of claim 3 , wherein performing the single thermal process reflows the second conductive connector.

5. The method of claim 3 , wherein the protective structure has a void disposed between the passive device and the redistribution structure.

6. The method of claim 5 , wherein the protective structure separates the void from the passive device, the redistribution structure, the second conductive connector, and the first pad.

7. The method of claim 5 , wherein the protective structure separates the void from the passive device and the redistribution structure, and the void exposes surfaces of the second conductive connector and the first pad.

8. The method of claim 5 , wherein the protective structure separates the void from the second conductive connector and the first pad, and the void exposes surfaces of the passive device and the redistribution structure.

9. The method of claim 5 , wherein the void exposes surfaces of the second conductive connector, the first pad, the passive device, and the redistribution structure.

10. A method comprising:

encapsulating an integrated circuit die with an encapsulant;

depositing a first dielectric layer over the encapsulant and the integrated circuit die;

forming a first metallization pattern extending along and through the first dielectric layer, the first metallization pattern electrically coupling the integrated circuit die;

depositing a second dielectric layer over the first metallization pattern;

forming a first pad and a second pad through the second dielectric layer, the first pad and the second pad electrically coupling the first metallization pattern;

adhering a passive device to the first pad and the second dielectric layer with an epoxy flux, the passive device comprising a first reflowable connector, the first reflowable connector being physically and electrically coupled to the first pad after adhering the passive device;

forming a non-epoxy flux on the second pad, the non-epoxy flux being different from the epoxy flux;

forming a second reflowable connector on the non-epoxy flux; and

performing a single thermal process to simultaneously cure the epoxy flux, remove the non-epoxy flux, reflow the first reflowable connector, and reflow the second reflowable connector.

11. The method of claim 10 further comprising:

dispensing the epoxy flux on the first pad with a first stencil, the first stencil having a first opening exposing the first pad.

12. The method of claim 11 wherein forming the non-epoxy flux on the second pad comprises:

dispensing the non-epoxy flux on the second pad with a second stencil, the second stencil having a second opening exposing the second pad, the second stencil having a recess covering the passive device.

13. The method of claim 10 , wherein after adhering the passive device, the epoxy flux has a main body disposed between the passive device and the second dielectric layer and a fillet extending along the second dielectric layer away from the main body, the main body having at least one void disposed therein.

14. The method of claim 13 , wherein the fillet of the epoxy flux extends away from the main body by a first distance, the first distance being from 1 μm to 200 μm.

15. The method of claim 10 further comprising:

attaching a package substrate to the second pad with the second reflowable connector; and

forming an underfill between the package substrate and the second dielectric layer, the underfill contacting sides of the epoxy flux and the passive device.

16. A method comprising:

encapsulating an integrated circuit die with an encapsulant;

forming a redistribution structure on the encapsulant, the redistribution structure being electrically connected to the integrated circuit die, the redistribution structure comprising a first pad and a second pad;

dispensing an epoxy flux on the first pad to form a protective structure;

pressing a passive device into the protective structure to physically couple the passive device to the first pad;

covering the passive device with a stencil, the stencil having an opening exposing the second pad;

cleaning the second pad through the opening in the stencil while the stencil covers the passive device; and

after cleaning the second pad, forming a first conductive connector on the second pad, wherein forming the first conductive connector comprises performing a single thermal process, the single thermal process curing the protective structure.

17. The method of claim 16 further comprising:

attaching a package substrate to the redistribution structure with the first conductive connector; and

forming an underfill between the package substrate and the redistribution structure, the underfill contacting sides of the protective structure and the passive device.

18. The method of claim 16 , wherein cleaning the second pad comprises:

dispensing a non-epoxy flux on the second pad, the single thermal process removing the non-epoxy flux.

19. The method of claim 16 , wherein the epoxy flux comprises a resin material and a flux material.

20. The method of claim 16 , wherein performing the single thermal process comprises:

heating the first conductive connector and the protective structure at a temperature in a range of 217° C. to 260° C. for a duration in a range of 30 seconds to 150 seconds.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2019
From: YU, JEN-JUI; PEI, HAO-JAN; CHEN, WEI-YU; CHANG, CHIA-LUN; LIN, HSIU-JEN; HSIEH, CHING-HUA
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 049644/0833 →
Continuity (2)
Provisional Application 62773482 · Nov 30, 2018
Related Publication 20200176387A1 · Jun 4, 2020
Cited By (2)
US 12,255,078 US 12,652,810