IP Library › Granted Patent US 11,127,644
Granted Patent B2
US 11,127,644 · App. 16/570,776 · Granted Sep 21, 2021

Planarization of semiconductor packages and structures resulting therefrom

Inventors: Chi-Yang Yu (Zhongli, TW); Hai-Ming Chen (Kaohsiung, TW); Yu-Min Liang (Zhongli, TW); Jung Wei Cheng (Hsinchu, TW); Chien-Hsun Lee (Chu-tung Town, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L23/18H01L21/31053H01L21/4857H01L21/56H01L21/561H01L21/6835H01L23/295H01L23/3128H01L25/0652H01L21/31058H01L21/568H01L21/6836H01L24/13H01L24/29H01L2221/68318H01L2221/68336H01L2221/68359H01L2221/68372H01L2221/68381H01L2224/18H01L2224/48091H01L2224/48227H01L2224/73267H01L2224/85203H01L2924/00014H01L2924/1203H01L2924/1304H01L2924/1436H01L2924/1461H01L2924/15311H01L2924/181
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Quick Facts
Patent No.
US 11,127,644
App. No.
16/570,776
Granted
Sep 21, 2021
Kind
B2
Abstract

An embodiment method includes encapsulating a semiconductor die in an encapsulant, planarizing the encapsulant, and depositing a polymer material on the encapsulant. The method further includes planarizing the polymer material and forming a metallization pattern on the polymer material. The metallization pattern electrically connects a die connector of the semiconductor die to a conductive feature disposed outside of the semiconductor die.

Claims (35)

1. A package comprising:

an integrated circuit die comprising a die connector;

an encapsulant disposed around the integrated circuit die;

a polymer material over at least a portion of the encapsulant, wherein a convex surface of the polymer material extends below a topmost surface of the encapsulant;

an impurity disposed at a top surface of the polymer material, a material of the impurity being different than the polymer material; and

a conductive line over the polymer material, the conductive line electrically connecting the die connector to a conductive feature, and a portion of the encapsulant is disposed between the die connector and the conductive feature.

2. The package of claim 1 , further comprising a polymer layer disposed between the conductive line and the polymer material, the impurity is disposed at an interface between the polymer material and the polymer layer.

3. The package of claim 2 , wherein the polymer layer further forms an interface with the encapsulant.

4. The package of claim 2 , wherein the polymer layer covers an entire top surface of the encapsulant.

5. The package of claim 1 , wherein the impurity is disposed at an interface between the conductive line and the polymer material.

6. The package of claim 1 , wherein a top surface of the die connector is disposed below a top surface of the encapsulant, the polymer material extending from the top surface of the encapsulant to the top surface of the die connector.

7. The package of claim 1 , wherein the impurity comprises silicon, aluminum, or a combination thereof.

8. A package comprising:

a semiconductor die;

a molding material encapsulating the semiconductor die, wherein the molding material comprises a hollow-core filler material;

a polymer material, wherein a filler material circumferentially surrounds a bottom portion of the polymer material, wherein the filler material is a same material as the hollow-core filler material; and

a conductive line electrically connected to the semiconductor die, the conductive line further overlying the molding material and the polymer material.

9. The package of claim 8 further comprising an impurity at a top surface of the polymer material.

10. The package of claim 9 , wherein the impurity comprises silicon or aluminum.

11. The package of claim 9 further comprising a polymer layer between the conductive line and the polymer material, wherein the impurity is at an interface between the polymer material and the polymer layer.

12. The package of claim 8 , wherein top surfaces of the polymer material and the molding material are substantially level.

13. The package of claim 12 further comprising a die connector electrically connecting the conductive line to the semiconductor die, a top surface of the die connector is substantially level with the molding material and the polymer material.

14. The package of claim 13 , wherein the polymer material physically contacts the die connector.

15. The package of claim 8 , wherein the conductive line physically contacts the polymer material.

16. The package of claim 8 , wherein the conductive line physically contacts the filler material.

17. A package comprising:

a first die;

a second die;

a molding compound between the first die and the second die, the molding compound comprising a filler material;

a polymer material having a top surface substantially planar with the molding compound;

a polymer layer over the polymer material, wherein an impurity is disposed at an interface between the polymer material and the polymer layer, wherein the impurity comprises silicon or aluminum; and

a conductive line over the polymer layer, the conductive line electrically connects the first die to the second die.

18. The package of claim 17 further comprising a dielectric material around a first die connector of the first die, the dielectric material is co-terminus with the first die.

19. The package of claim 17 , wherein the filler material surrounds a bottom portion of the polymer material.

20. The package of claim 17 , wherein the filler material physically contacts a second die connector of the second die.

Continuity (3)
Division 15908520 · Feb 28, 2018
Provisional Application 62586558 · Nov 15, 2017
Related Publication 20200006171A1 · Jan 2, 2020
Cited By (1)
US 12,469,756