FinFETs having epitaxial capping layer on fin and methods for forming the same
A FinFET and methods for forming a FinFET are disclosed. A method includes forming a semiconductor fin on a substrate, implanting the semiconductor fin with dopants, and forming a capping layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a dielectric on the capping layer, and forming a gate electrode on the dielectric.
1. A method comprising:
implanting dopants into a fin extending from a substrate, the fin being surrounded by an isolation region;
after the implanting dopants into the fin, etching the isolation region to expose sidewalls of the fin;
performing a surface treatment process on the exposed sidewalls and a top surface of the fin; and
after performing the surface treatment process, epitaxially growing a capping layer on the top surface and the exposed sidewalls of the fin, wherein the capping layer covers a first portion of the exposed sidewalls of the fin, and wherein a second portion of the exposed sidewalls of the fin is free from the capping layer.
2. The method of claim 1 , wherein the performing the surface treatment process comprises performing a dry etch process on the exposed sidewalls and the top surface of the fin, the dry etch process comprising an etchant gas of hydrogen chloride (HCl) or chlorine (Cl 2 ).
3. The method of claim 1 , wherein the implanting dopants into the fin comprises implanting n-type or p-type impurities into the fin.
4. The method of claim 3 , further comprising performing a pre-amorphization implant process before the implanting dopants into the fin, wherein the performing the pre-amorphization implant process comprises implanting germanium, carbon, fluorine, or indium into the fin.
5. The method of claim 3 , further comprising annealing the fin after the implanting dopants into the fin, wherein the annealing the fin and the implanting dopants into the fin form twin plane defects in the fin, wherein the twin plane defects occur at a (111) crystal orientation.
6. The method of claim 1 , further comprising forming a gate dielectric over the fin and forming a gate electrode over the gate dielectric.
7. The method of claim 6 , wherein the gate dielectric is in physical contact with the capping layer and the fin.
8. The method of claim 7 , wherein the gate electrode is in physical contact with the isolation region.
9. The method of claim 1 , wherein the capping layer has a material composition the same as a material composition of the fin.
10. A method comprising:
forming a fin over a substrate;
forming an isolation region over the substrate, the isolation region surrounding the fin;
implanting dopants into the fin;
after implanting dopants into the fin, etching the isolation region to expose a first portion of the fin;
treating the first portion of the fin with a dry etch process;
after treating the first portion of the fin, epitaxially growing a capping layer on a top surface and sidewalls of the first portion of the fin; and
forming a gate electrode over the capping layer, the fin, and the isolation region, wherein the gate electrode is formed in physical contact with the isolation region.
11. The method of claim 10 , further comprising:
forming a gate dielectric on the capping layer, wherein the gate electrode is formed on the gate dielectric and the isolation region.
12. The method of claim 11 further comprising:
forming a source region in the fin; and
forming a drain region in the fin, the source region being on an opposite side of the gate electrode than the drain region, the capping layer extending across the top surface of the fin from the source region to the drain region.
13. The method of claim 10 , wherein a bottom surface of the capping layer adjoins a top surface of the isolation region.
14. The method of claim 10 , wherein implanting dopants into the fin causes twin plane defects in the fin, the capping layer being grown over the twin plane defects.
15. The method of claim 10 further comprising:
before forming a fin over the substrate, doping the substrate with dopants; and
forming a second semiconductor fin on the doped substrate, before implanting dopants into the semiconductor fin, the isolation region surrounding the second semiconductor fin, the isolation region contacting opposite sidewalls of both the semiconductor fin and the second semiconductor fin.
16. The method of claim 10 further comprising:
after implanting dopants into the fin and before etching the isolation region, performing an anneal process on the fin.
17. A method comprising:
forming a fin on a substrate;
forming an isolation region on the substrate, the isolation region surrounding the fin;
implanting the fin with dopants, the implanting the fin with dopants causing twin plane defects in the fin;
epitaxially growing a capping layer on a top surface and sidewalls of the fin, the capping layer being grown over the twin plane defects; and
after epitaxially growing the capping layer, forming a gate structure on the capping layer, wherein the gate structure is formed in physical contact with the capping layer and portions of the sidewalls of the fin exposed after epitaxially growing the capping layer.
18. The method of claim 17 , wherein a bottom surface of the capping layer is spaced apart from a top surface of the isolation region.
19. The method of claim 17 further comprising:
forming a source region in the fin; and
forming a drain region in the fin, the gate structure being interposed between the drain region and the source region, the capping layer extending across the top surface of the fin from the source region to the drain region.
20. The method of claim 17 , wherein epitaxially growing the capping layer on the top surface and the sidewalls of the fin comprises homoepitaxially growing the capping layer from the top surface and the sidewalls of the fin.