Semiconductor arrangement with capacitor and method of fabricating the same
A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.
1. A semiconductor arrangement, comprising:
a first dielectric layer;
a first metal structure in the first dielectric layer;
a second dielectric layer over the first dielectric layer, wherein:
the second dielectric layer has a first recess defined by a first pair of sidewalls of the second dielectric layer and a second recess defined by a second pair of sidewalls of the second dielectric layer, and
the first recess and the second recess have a same cross-sectional profile;
a contact in the first recess defined by the second dielectric layer, wherein the contact has a homogenous composition and completely fills the first recess;
a capacitor, comprising:
a first electrode in the second recess defined by the second dielectric layer and overlying the first metal structure;
an insulating layer in the second recess defined by the second dielectric layer and over the first electrode; and
a second electrode in the second recess defined by the second dielectric layer and over the insulating layer; and
a pickup contact over and extending through the second electrode, wherein the pickup contact directly contacts a first sidewall of the second electrode and a first sidewall of the insulating layer.
2. The semiconductor arrangement of claim 1 , wherein an open space void of material is defined between a second sidewall of the second electrode and a third sidewall of the second electrode.
3. The semiconductor arrangement of claim 2 , wherein a fourth sidewall of the second electrode and a fifth sidewall of the second electrode directly contact the insulating layer.
4. The semiconductor arrangement of claim 1 , comprising:
a bit line in the first dielectric layer.
5. The semiconductor arrangement of claim 1 , comprising:
a third dielectric layer, wherein the first electrode directly contacts a sidewall of the second dielectric layer and a sidewall of the third dielectric layer.
6. The semiconductor arrangement of claim 1 , comprising:
an etch stop layer over the second electrode, wherein an open space void of material is defined between the etch stop layer and the second electrode.
7. The semiconductor arrangement of claim 6 , wherein the etch stop layer directly contacts with a second sidewall of the insulating layer.
8. The semiconductor arrangement of claim 7 , wherein the etch stop layer directly contacts with a second sidewall of the second electrode.
9. The semiconductor arrangement of claim 6 , wherein the etch stop layer directly contacts with a second sidewall of the second electrode.
10. The semiconductor arrangement of claim 6 , wherein the pickup contact extends through the etch stop layer.
11. A semiconductor arrangement, comprising:
a plurality of dielectric layers;
a capacitor, comprising:
a first electrode extending through at least two of the plurality of dielectric layers;
an insulating layer over the first electrode and extending through the at least two of the plurality of dielectric layers; and
a second electrode over the insulating layer and extending through the at least two of the plurality of dielectric layers;
an etch stop layer over the second electrode, wherein:
the etch stop layer directly contacts a first sidewall of the insulating layer, and
an open space void of material is defined between the second electrode and the etch stop layer; and
a pickup contact extending through the etch stop layer and directly contacting a first sidewall of the second electrode and a second sidewall of the insulating layer.
12. The semiconductor arrangement of claim 11 , wherein the open space is defined between a second sidewall of the second electrode and a third sidewall of the second electrode.
13. The semiconductor arrangement of claim 12 , wherein a fourth sidewall of the second electrode and a fifth sidewall of the second electrode directly contact the insulating layer.
14. The semiconductor arrangement of claim 11 , wherein the etch stop layer directly contacts a second sidewall of the second electrode.
15. The semiconductor arrangement of claim 11 , wherein a bottommost surface of the etch stop layer is above a topmost surface of an uppermost dielectric layer of the plurality of dielectric layers.
16. The semiconductor arrangement of claim 11 , wherein the open space extends through the at least two of the plurality of dielectric layers.
17. The semiconductor arrangement of claim 11 , wherein the etch stop layer comprises at least one of SiC, SiN, SiCN, SiCO, or CN.
18. A semiconductor arrangement, comprising:
a first dielectric layer and a second dielectric layer over the first dielectric layer; and
a capacitor, comprising:
a first electrode extending through the first dielectric layer and the second dielectric layer;
an insulating layer over the first electrode; and
a second electrode over the insulating layer, wherein:
an open space void of material is defined by the second electrode and extends through the first dielectric layer and the second dielectric layer, wherein:
a first portion of the open space extending through the first dielectric layer has a first width,
a second portion of the open space extending through the second dielectric layer has a second width less than the first width,
a third portion of the open space extending through the second dielectric layer has a third width greater than the second width, and
the third portion is over the second portion.
19. The semiconductor arrangement of claim 18 , comprising:
an etch stop layer over the second electrode, wherein the open space is further defined by the etch stop layer.
20. The semiconductor arrangement of claim 19 , wherein the etch stop layer directly contacts a sidewall of the insulating layer.