IP Library › Granted Patent US 11,233,001
Granted Patent B2
US 11,233,001 · App. 16/712,347 · Granted Jan 25, 2022

Adhesive layer bonding a plurality of substrates having a fillet raised portion

Inventors: Shota Miki (Nagano, JP); Naoki Kobayashi (Nagano, JP)
Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
H01L23/49822H01L23/3128H01L23/49816H01L23/522H01L24/13H01L24/14H01L24/16H01L24/17H01L24/29H01L24/81H01L25/0657H01L25/50
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Quick Facts
Patent No.
US 11,233,001
App. No.
16/712,347
Granted
Jan 25, 2022
Kind
B2
Abstract

An interconnect board includes: a first substrate; a second substrate having an outer shape smaller than an outer shape of the first substrate and mounted on the first substrate; and an adhesive layer bonding the first substrate and the second substrate together and having a fillet contacting a side surface of the second substrate. The fillet has a raised portion raised from a level of a top surface of the second substrate to a level higher than the top surface of the second substrate.

Claims (44)

1. An interconnect board comprising:

a first substrate;

a second substrate having an outer shape smaller than an outer shape of the first substrate and mounted on the first substrate; and

an adhesive layer bonding the first substrate and the second substrate together and having a fillet contacting a side surface of the second substrate, wherein

the first substrate has a first electrode on a surface opposing the second substrate,

the second substrate has a second electrode on a first surface opposing the first substrate, and a third electrode on a second surface opposite to the first surface,

the first electrode and the second electrode are joined through a solder,

the fillet has a raised portion raised from a level of the second surface of the second substrate to a level higher than the second surface of the second substrate and not covering the third electrode,

the raised portion has a side surface adjacent to an outer periphery of the second surface and inclined obliquely upward from a plane where the second surface is located at areas outside the side surface of the second substrate, and

the adhesive layer is filled between the first substrate and the second substrate and covers the first surface of the second substrate and the solder.

2. The interconnect board according claim 1 , wherein the raised portion is formed as a frame-like portion arranged along the outer periphery of the second substrate and forms a bottomed space in combination with the second surface of the second substrate.

3. A semiconductor package comprising:

the interconnect board according to claim 2 ;

a first electronic component mounted on the second surface of the second substrate; and

an underfill resin arranged in the bottomed space.

4. The semiconductor package according claim 3 , further comprising a second electronic component mounted on the first substrate, wherein

the second electronic component is exposed from the adhesive layer.

5. The interconnect board according claim 1 , wherein the first substrate is a multilayer build-up substrate.

6. The interconnect board according claim 1 , wherein the second substrate is an interposer substrate.

7. The interconnect board according claim 1 , wherein the second substrate is electrically connected with the first substrate through the solder.

8. The interconnect board according claim 1 , wherein the adhesive layer is made of a thermosetting resin.

9. The interconnect board according claim 1 , wherein the raised portion does not cover the second surface of the second substrate.

10. The interconnect board according claim 1 , wherein a top portion of the raised portion that is not obliquely inclined is located only outside the side surface of the second substrate.

11. The interconnect board according claim 1 , wherein the adhesive layer is integrally connected to the fillet.

12. The interconnect board according claim 1 , wherein the side surface of the raised portion is continuously provided to the outer periphery of the second surface and inclined obliquely upward from the plane where the second surface is located at areas outside the side surface of the second substrate.

13. An interconnect board comprising:

a first substrate;

a second substrate having an outer shape smaller than an outer shape of the first substrate and mounted on the first substrate; and

an adhesive layer bonding the first substrate and the second substrate together and having a fillet contacting a side surface of the second substrate, wherein

the first substrate has a first electrode on a surface opposing the second substrate,

the second substrate has a second electrode on a first surface opposing the first substrate, and a third electrode on a second surface opposite to the first surface,

the first electrode and the second electrode are joined through a solder,

the fillet has a raised portion raised from a level of the second surface of the second substrate to a level higher than the second surface of the second substrate and not covering the third electrode,

the raised portion has a side surface adjacent to an outer periphery of the second surface and inclined obliquely upward from a plane where the second surface is located at areas outside the side surface of the second substrate, and

between the first substrate and the second substrate, the adhesive layer is filled and an electronic component is not disposed.

14. An interconnect board comprising:

a first substrate;

a second substrate having an outer shape smaller than an outer shape of the first substrate and mounted on the first substrate; and

an adhesive layer bonding the first substrate and the second substrate together and having a fillet contacting a side surface of the second substrate, wherein

the first substrate has a first electrode on a surface opposing the second substrate,

the second substrate has a second electrode on a first surface opposing the first substrate, and a third electrode on a second surface opposite to the first surface,

the first electrode and the second electrode are joined through a solder,

the fillet has a raised portion raised from a level of the second surface of the second substrate to a level higher than the second surface of the second substrate and not covering the third electrode, and

the raised portion has a side surface adjacent to an outer periphery of the second surface and inclined obliquely upward from a plane where the second surface is located at areas outside the side surface of the second substrate, a top portion of the raised portion being rounded in a sectional shape.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2019
From: MIKI, SHOTA; KOBAYASHI, NAOKI
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 051268/0908 →
Priority Claims (1)
JP JP2018-243631 · Dec 26, 2018 · national
Continuity (1)
Related Publication 20200211946A1 · Jul 2, 2020
Cited By (1)
US 12,733,534