Multilayer pillar for reduced stress interconnect and method of making same
A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
1. A method of forming an interconnect pillar between a chip and a substrate, the method comprising:
forming a first copper layer connected to the chip by a barrier and adhesion layer;
forming a seed layer contacting the barrier and adhesion layer and contacting the first copper layer, the seed layer being chromium copper;
forming a second copper layer connected to a via in the substrate by a solder layer; and
forming an intermediate layer interposed between the first copper layer and the second copper layer,
wherein the intermediate layer is aluminum.
2. The method of claim 1 , wherein the intermediate layer is planar and slides or tilts in response to the intermediate layer being heated.
3. The method of claim 1 , further comprising forming a second intermediate layer between the second copper layer and a third copper layer, and the third copper layer is between the intermediate layer and the second intermediate layer.
4. The method of claim 1 , wherein the intermediate layer is planar and slides or tilts with the chip in response to the intermediate layer being heated.
5. The method of claim 1 , wherein a sidewall of the first copper layer is aligned with a sidewall of the intermediate layer.
6. The method of claim 1 , wherein a sidewall of the intermediate layer is aligned with a sidewall of the second copper layer.
7. The method of claim 1 , wherein a vertical sidewall of the first copper layer is aligned with a vertical sidewall of the second copper layer.
8. The method of claim 1 , further comprising forming a protective layer interposed at an interface between a surface of the intermediate layer and the first copper layer.
9. The method of claim 1 , wherein the barrier and adhesion layer comprises titanium tungsten.
10. The method of claim 9 , wherein the via includes nickel phosphorous material.
11. The method of claim 10 , wherein the intermediate layer has a modulus of elasticity less than copper.