System idle time reduction methods and apparatus
An apparatus is provided that includes a memory die including a pipeline circuit coupled to a memory structure. The memory die is configured to execute a first command by receiving in the pipeline circuit data to be written to the memory structure, processing the received data in the pipeline circuit and providing the processed data to the memory structure, predicting that the pipeline circuit has completed processing the received data, and ending execution of the first command based on the prediction.
1. An apparatus comprising:
a memory die comprising a pipeline circuit coupled to a memory structure, the memory die configured to:
execute a first command by:
receiving in the pipeline circuit data to be written to the memory structure;
processing the received data in the pipeline circuit and providing the processed data to the memory structure;
predicting that the pipeline circuit has completed processing the received data; and
ending execution of the first command based on the prediction.
2. The apparatus of claim 1 , wherein the memory die is further configured to wait until the memory die ends executing the first command before starting to execute a second command.
3. The apparatus of claim 2 , wherein the first command comprises a data-in command, and the second command comprises any of a data-in command, a data-out command, a dummy command, and an erase command.
4. The apparatus of claim 1 , wherein the predicting further comprises determining that a source of the received data has completed sending data to be written to the memory die.
5. The apparatus of claim 1 , wherein the memory die comprises a peripheral region that includes the pipeline circuit and a memory core that includes the memory structure.
6. The apparatus of claim 1 , wherein the pipeline circuit is configured to accumulate the received data, and provide the accumulated data for programming on the memory structure.
7. The apparatus of claim 1 , wherein the memory die further comprises intermediate latches coupled to the pipeline circuit and the memory structure, and wherein executing the first command comprises storing the processed data in the intermediate latches, and programming the memory structure based on the stored data.
8. The apparatus of claim 1 , further comprising a controller configured to provide the pipeline circuit with the data to be written.
9. The apparatus of claim 1 , further comprising a first semiconductor die that includes the memory die, and a second semiconductor die that comprises a controller configured to provide the data to be written to the pipeline circuit.
10. The apparatus of claim 9 , wherein the first semiconductor die is directly bonded to the second semiconductor die.
11. A method comprising:
receiving a first command at a memory die that comprises a pipeline circuit coupled to a memory structure;
processing data associated with the first command in the pipeline circuit and providing the processed data for writing to the memory structure; and
ending execution of the first command without determining that the pipeline circuit has completed processing the data.
12. The method of claim 11 , further comprising receiving a second command at the memory die before the pipeline circuit has completed processing the data.
13. The method of claim 11 , further comprising waiting to end execution of the first command before starting to execute a second command received at the memory die.
14. The method of claim 13 , wherein the first command comprises a data-in command, and the second command comprises any of a data-in command, a data-out command, a dummy command, and an erase command.
15. The method of claim 11 , further comprising ending execution of the first command after determining that a source of the data has completed sending data to be written to the memory die.
16. The method of claim 11 , further comprising accumulating the data in the pipeline circuit, and providing the accumulated data for programming on the memory structure.
17. The method of claim 11 , further comprising:
storing the processed data in intermediate latches coupled to the pipeline circuit and the memory structure; and
programming the memory structure based on the stored data.
18. The method of claim 11 , wherein the memory die comprises a first semiconductor die directly bonded to a second semiconductor die that is configured to provide the first command and the data.
19. A system comprising:
a first semiconductor die comprising a controller;
a second semiconductor die bonded to the first semiconductor die, the second semiconductor die comprising a memory die comprising a peripheral region and a memory core that includes non-volatile memory cells, the peripheral region comprising circuitry configured to:
receive a first command and data associated with the first command sent from the controller;
execute the first command by accumulating chunks of the received data to be written to the non-volatile memory cells;
detect that the controller has stopped sending data to the memory die; and
end execution of the first command based on the detection without determining that the circuitry has completed accumulating the data.
20. The system of claim 19 , wherein the circuitry is further configured to:
receive a second command from the controller; and
waiting to end execution of the first command before starting to execute the second command.