IP Library › Granted Patent US 11,302,595
Granted Patent B2
US 11,302,595 · App. 17/025,106 · Granted Apr 12, 2022

Package assembly and method for manufacturing the same, package assembly of buck converter

Inventors: Ke Dai (Hangzhou, CN); Jian Wei (Hangzhou, CN); Jiajia Yan (Hangzhou, CN)
Assignee: Hefei Silergy Semiconductor Technology Co., Ltd.
H01L23/36H01L21/50H01L23/5385H01L23/5386H01L23/60H02M3/1582
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Quick Facts
Patent No.
US 11,302,595
App. No.
17/025,106
Granted
Apr 12, 2022
Kind
B2
Abstract

A package assembly can include: a die electrically connected to outer pins of the package assembly; an electronic component located above the die and electrically connected to the die, wherein the electronic component is connected to the outer pins of the package assembly through conductive pillars; and a heat dissipation structure located between the die and the electronic component to facilitate heat dissipation of the electronic component, where the heat dissipation structure physically isolates the die and the electronic component such that electromagnetic interference from the electronic component to the die is substantially prevented.

Claims (28)

1. A package assembly, comprising:

a) a die electrically connected to outer pins of the package assembly;

b) an electronic component located above the die and electrically connected to the die, wherein the electronic component is connected to the outer pins of the package assembly through conductive pillars, and wherein the electronic component is one of an inductor, a transformer, a resistor, and a capacitor; and

c) a heat dissipation structure located between the die and the electronic component to facilitate heat dissipation of the electronic component, wherein the heat dissipation structure physically isolates the die and the electronic component such that electromagnetic interference from the electronic component to the die is substantially prevented.

2. The package assembly of claim 1 , wherein at least part of the heat dissipation structure is exposed outside of the package assembly in order to export heat generated by the electronic component.

3. The package assembly of claim 1 , wherein the heat dissipation structure comprises a first part located above the die, and a second part extending towards an outside of the package assembly and connected to the first part.

4. The package assembly of claim 3 , wherein the second part of the heat dissipation structure is in contact with the outer pins of the package assembly.

5. The package assembly of claim 3 , wherein:

a) the package assembly further comprises a pad structure of the electronic component;

b) the pad structure comprises a metal layer and a soldered layer on the metal layer; and

c) the pad structure is connected to conductive pillars to realize electrical connection between the electronic component and the outer pins of the package assembly.

6. The package assembly of claim 5 , wherein a shape of the first part of the heat dissipation structure is set to isolate it from the pad structures and increases a horizontal area of the heat dissipation structure.

7. The package assembly of claim 5 , wherein the first part of the heat dissipation structure is set along peripheries of the pad structures.

8. The package assembly of claim 3 , wherein the first part of the heat dissipation structure has uniform thickness throughout.

9. The package assembly of claim 5 , wherein a thickness of the first part of the heat dissipation structure is set such that a plane of a middle part of the first part of the heat dissipation structure is higher than a plane of parts adjacent to the pad structures on two sides thereof, in order to prevent the soldered layer from being soldered together with the heat dissipation structure.

10. The package assembly of claim 5 , wherein the heat dissipation structure comprises at least two mutually detached substructures, and at least one of the substructure is conformal to the metal layer of one of pad structure of the electronic component.

11. The package assembly of claim 9 , wherein the middle part of the first part of the heat dissipation structure is on a same plane as the metal layer.

12. The package assembly of claim 1 , wherein the heat dissipation structure is connected to a ground potential pin to increase heat dissipation of the electronic component.

13. The package assembly of claim 5 , wherein a back surface of the die comprises a layer of insulator film, in order to insulate the heat dissipation structure and pad structures from the die.

14. The package assembly of claim 1 , further comprising a frame for installing the die, wherein the frame comprises the outer pins of the package assembly.

15. The package assembly of claim 14 , wherein the frame is formed by a redistribution layer (RDL) process.

16. A method of manufacturing a package assembly, the method comprising:

a) providing a die electrically connected to outer pins of the package assembly;

b) installing an electronic component above the die that is electrically connected to the die, wherein the electronic component is connected to the outer pins of the package assembly through conductive pillars, and wherein the electronic component is one of an inductor, a transformer, a resistor, and a capacitor; and

c) forming a heat dissipation structure between the electronic component and the die to facilitate heat dissipation of the electronic component, wherein the heat dissipation structure physically isolates the electronic component and the die such that electromagnetic interference from the electronic component to the die is substantially prevented.

17. The method of claim 16 , further comprising, prior to installing the electronic component, forming a pad structure of the electronic component comprising forming a metal layer and a soldered layer located on the metal layer such that the metal layer neighbors a back surface of the die.

18. The method of claim 17 , wherein the forming the metal layer comprises forming a first part of the heat dissipation structure such that the first part neighbors the back surface of the die.

19. The method of claim 17 , further comprising forming the conductive pillars connected to the pad structure such that the electronic component is connected to the outer pins of the package assembly by the pad structure and conductive pillars.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2021
From: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
To: HEFEI SILERGY SEMICONDUCTOR TECHNOLOGY CO., LTD.
Reel/Frame 058912/0311 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2020
From: DAI, KE; WEI, JIAN; YAN, JIAJIA
To: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD
Reel/Frame 053815/0983 →
Priority Claims (1)
CN 201910927320.4 · Sep 27, 2019 · national
Continuity (1)
Related Publication 20210098329A1 · Apr 1, 2021