Dynamic staggering for programming in nonvolatile memory

1. An apparatus, comprising:

a controller;

a plurality of memory dies operably connected to and controlled by the controller, wherein each of the memory dies draws a current from a current source during a program operation; and

the controller being configured to:

receive clock signals from the memory dies, each clock signal being associated with a time point, which is a fixed time before peak current demand during the program operation of a corresponding memory die;

count a number of the clock signals received by the controller within a threshold time to determine a count value of memory dies that will hit peak current demand within the threshold time; and

dynamically stagger the corresponding program operation of at least one of the memory dies relative to the corresponding program operation of at least one other of the memory dies when the count value reaches a maximum count value within the threshold time to reduce total peak current demand by the memory dies.

2. The apparatus of claim 1 , wherein the controller is configured to reset the count value to zero when the threshold time has elapsed.

3. The apparatus of claim 2 , wherein the controller is further configured to restart a timer counting out the threshold time when a new clock signal is received.

4. The apparatus of claim 3 , wherein the timer count starts at the threshold time and counts down to zero.

5. The apparatus of claim 4 , wherein the controller is further configured to determine a loop count for each memory die of the plurality of memory dies to determine a number of times each memory die of the plurality of memory dies has looped through the programming operation.

6. The apparatus of claim 5 , wherein, for each memory die, the controller compares the loop count versus a minimum loop value and a maximum loop value and the loop count must be between or equal to one of the minimum loop value and the maximum loop value to trigger dynamic staggering.

7. The apparatus of claim 6 , wherein the controller is further configured to receive the corresponding loop count and the corresponding clock signal from each memory die over a communication bus.

8. The apparatus of claim 1 wherein the maximum count value is equal to a number of the plurality of memory dies.

9. The apparatus of claim 1 , wherein the controller is configured to dynamically stagger a first memory die of the plurality of memory dies with a first delay and a second memory die of the plurality of memory dies with a second delay, and the first delay is different than the second delay.

10. A dynamic staggering method for nonvolatile memory, comprising:

receiving, at a memory controller operably connected to a plurality of memory dies, clock signals that each indicate a programming operation at a corresponding memory die of the plurality of memory dies;

starting a timer upon receipt of a first clock signal from a first memory die of the plurality of memory dies;

counting a number of the clock signals from the plurality of memory dies received by the memory controller within a threshold time of the timer, each clock signal being associated with a time point, which is a fixed time before peak current demand during the programming operation of the corresponding memory die;

determining if the counted number of the clock signals exceeds a maximum count within the threshold time;

if the counted number of the clock signals does not exceed the maximum count within the threshold time, performing previously scheduled operations on each of the plurality of memory dies; and

if the counted number of the clock signals exceeds the maximum count within the threshold time, dynamically staggering the corresponding program operation of at least one memory die of the plurality of memory dies relative to at least one other memory die at least one other memory die of the plurality of memory dies to prevent the plurality of memory dies from operating synchronously during programming operations of the memory dies.

11. The method of claim 10 , further comprising resetting the counted number of the clock signals to zero when the threshold time has elapsed.

12. The method of claim 11 , wherein starting the timer includes starting the timer at the threshold time and counting down to zero.

13. The method of claim 10 , further comprising determining a loop count for each memory die of the plurality of memory dies.

14. The method of claim 13 , wherein determining the loop count for each memory die further includes comparing the loop count versus a minimum loop value and a maximum loop value and the loop count must be between or equal to one of the minimum loop value and the maximum loop value to trigger dynamic staggering.

15. A circuit for operating a plurality of memory dies, comprising:

a bus configured to connect with a plurality of memory dies and wherein clock signals can be received via the bus from the plurality of memory dies, each clock signal being associated with a time point, which is a fixed time before peak current demand during a programming operation of a corresponding memory die of the plurality of memory dies;

control circuitry configured to:

count the number of the clock signals received within a threshold time to determine a count value, and

communicate a signal via the bus to dynamically stagger the corresponding program operation of at least one of the memory dies relative to the corresponding program operation of at least one other memory die of the plurality of memory dies when the count value reaches a maximum count value within a threshold time.

16. The circuit as set forth in claim 15 , wherein the circuit is further configured to reset the count value to zero when the threshold time has elapsed.

17. The circuit as set forth in claim 16 , wherein the circuit is further configured to restart a timer counting out the threshold time when a new clock signal is received.

18. The circuit as set forth in claim 17 , wherein the timer count starts at the threshold time and counts down to zero.