Three-dimensional memory device employing thinned insulating layers and methods for forming the same

1. A three-dimensional memory device comprising:

an alternating stack of insulating layers and word lines located over a substrate; and

a memory opening fill structure extending through the alternating stack,

wherein:

the memory opening fill structure comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film;

the word lines are thicker than the insulating layers;

the memory film comprises a silicon oxide blocking dielectric layer; and

an outer sidewall of the silicon oxide blocking dielectric layer continuously extends vertically from a topmost word line within the alternating stack to a bottommost word line within the alternating stack, and has a laterally undulating vertical cross-sectional profile in which first vertical sidewall segments of the silicon oxide blocking dielectric layer contacting the insulating layers are laterally offset along a horizontal direction outward with respective to a vertical plane including second vertical sidewall segments of the silicon oxide blocking dielectric layer located at levels of the word lines.

2. The three-dimensional memory device of claim 1 , wherein the memory film further comprises:

a charge storage material contacting an inner sidewall of the silicon oxide blocking dielectric layer; and

a tunneling dielectric layer contacting an inner sidewall of the charge storage material.

3. The three-dimensional memory device of claim 1 , wherein an entirety of an inner cylindrical sidewall of the silicon oxide blocking dielectric layer has a straight vertical cross-sectional profile and vertically extends through each of the insulating layers and through each of the word lines within the alternating stack.

4. The three-dimensional memory device of claim 3 , wherein:

the first vertical sidewall segments are laterally spaced from the inner cylindrical sidewall of the silicon oxide blocking dielectric layer by a first thickness; and

the second vertical sidewall segments are laterally spaced from the inner cylindrical sidewall of the silicon oxide blocking dielectric layer by a second thickness that is less than the first thickness.

5. The three-dimensional memory device of claim 1 , wherein:

one of the second vertical sidewall segments of the outer sidewall of the silicon oxide blocking dielectric layer is connected to a pair of first vertical sidewall segments through a pair of annular tapered connecting surface segments; and

each the pair of annular tapered connecting surfaces segments has a respective concave tapered surface.

6. The three-dimensional memory device of claim 5 , wherein each of the concave tapered surfaces has a radius of curvature that is the same as a lateral offset distance between the second vertical sidewall segments and the first vertical sidewall segments.

7. The three-dimensional memory device of claim 5 , wherein:

each of the word lines is spaced from the silicon oxide blocking dielectric layer by a respective backside blocking dielectric layer;

one of the second vertical sidewall segments of the outer sidewall of the silicon oxide blocking dielectric layer contacts a vertical sidewall of one of the backside blocking dielectric layers; and

the pair of annular tapered connecting surface segments contacts convex tapered surfaces of the one of the backside blocking dielectric layers.

8. The three-dimensional memory device of claim 1 , wherein:

each word line has a vertical cylindrical sidewall that laterally surrounds the memory opening fill structure, an upper convex surface adjoined to an upper end of the vertical cylindrical sidewall, and a lower convex surface adjoined to a lower end of the vertical cylindrical sidewall; and

the three-dimensional memory device further comprises a source select gate electrode which lacks upper and lower convex surfaces, wherein the source select gate electrode is located below the word lines.

9. The three-dimensional memory device of claim 8 , wherein the memory opening fill structure comprises:

a pedestal channel portion contacting a top surface of a semiconductor material layer located in, or over, the substrate; and

a tubular dielectric spacer comprising a dielectric oxide material of a semiconductor material of the pedestal channel portion.

10. The three-dimensional memory device of claim 1 , further comprising air gaps that are at least partially surrounded by the insulating layers.