Three-dimensional memory device including multi-tier moat isolation structures and methods of making the same

1. A three-dimensional memory device comprising:

a first-tier alternating stack of first insulating layers and first electrically conductive layers located over a semiconductor material layer;

a second-tier alternating stack of second insulating layers and second electrically conductive layers located over the first alternating stack;

memory stack structures vertically extending through the second-tier alternating stack and the first-tier alternating stack;

a first dielectric moat structure vertically extending through the first-tier alternating stack and laterally surrounding a first vertically alternating sequence of first insulating plates and first dielectric material plates;

a plurality of dielectric pillar structures vertically extending through the second-tier alternating stack and contacting a top surface of the first dielectric moat structure; and

at least one through-memory-level interconnection via structure vertically extending at least from a horizontal plane including a top surface of the second-tier alternating stack, through the first vertically alternating sequence of first insulating plates and first dielectric material plates, and down to a respective metal interconnect structure underlying a horizontal plane including a bottom surface of the semiconductor material layer.

2. The three-dimensional memory device of claim 1 , wherein a combination of the first dielectric moat structure and the plurality of dielectric pillar structures consists of a single continuously-extending dielectric material portion having a uniform material composition throughout.

3. The three-dimensional memory device of claim 1 , further comprising a second dielectric moat structure vertically extending through the second-tier alternating stack and laterally surrounding a second vertically alternating sequence of second insulating plates and second dielectric material plates and overlying the first vertically alternating sequence of first insulating plates and first dielectric material plates.

4. The three-dimensional memory device of claim 3 , wherein a bottom periphery of outer sidewalls of the second dielectric moat structure is laterally recessed inward relative to a top periphery of inner sidewalls of the first dielectric moat structure.

5. The three-dimensional memory device of claim 3 , wherein the at least one through-memory-level interconnection via structure vertically extends through the second vertically alternating sequence of second insulating plates and second dielectric material plates.

6. The three-dimensional memory device of claim 3 , wherein:

outer sidewalls of the first dielectric moat structure contact the first insulating layers of the first-tier alternating stack; and

outer sidewalls of the second dielectric moat structure contact the second insulating layers of the second-tier alternating stack.

7. The three-dimensional memory device of claim 3 , wherein:

each of the first insulating plates is vertically spaced from a top surface of the semiconductor material layer by a same vertical distance as a respective first insulating layer in the first-tier alternating stack is from the top surface of the semiconductor material layer; and

each of the second insulating plates is vertically spaced from the top surface of the semiconductor material layer by a same vertical distance as a respective second insulating layer in the second-tier alternating stack is from the top surface of the semiconductor material layer.

8. The three-dimensional memory device of claim 3 , wherein a bottom surface of the second dielectric moat structure is located above, or at, a horizontal plane including a topmost surface of the first-tier alternating stack, or extends into the first-tier alternating stack and is located above at least one layer within the first-tier alternating stack.

9. The three-dimensional memory device of claim 1 , further comprising:

a semiconductor substrate underlying the semiconductor material layer;

semiconductor devices having sources, drains, and channel regions formed in the semiconductor substrate and gates formed on the semiconductor substrate;

lower-level dielectric material layers overlying the semiconductor devices and underlying the semiconductor material layer; and

lower-level metal interconnect structures embedded in the lower-level dielectric material layers, wherein each of the at least one through-memory-level interconnection via structure contacts a respective one of the lower-level metal interconnect structures.

10. The three-dimensional memory device of claim 9 , wherein:

the semiconductor material layer contains an opening in an area that underlies the first vertically alternating sequence of first insulating plates and first dielectric material plates; and

the at least one through-memory-level interconnection via structure extends through the opening in the semiconductor material layer.

11. The three-dimensional memory device of claim 1 , wherein:

the first-tier alternating stack and the second-tier alternating stack laterally extend along a first horizontal direction and have a uniform width along a second horizontal direction that is perpendicular to the first horizontal direction; and

the three-dimensional memory device comprises a pair of backside trench fill structures laterally extending along the first horizontal direction, laterally spaced from each other along the second horizontal direction, and contacting respective sidewalls of the first-tier alternating stack and the second-tier alternating stack.

12. The three-dimensional memory device of claim 1 , wherein:

each of the memory stack structures comprises a respective memory film and a respective vertical semiconductor channel; and

each of the vertical semiconductor channels contacts the semiconductor material layer.

13. The three-dimensional memory device of claim 1 , further comprising support pillar structures comprising a same dielectric material as the first dielectric moat structure and as the plurality of dielectric pillar structures, and vertically extending through the first-tier alternating stack and the second-tier alternating stack.

14. The three-dimensional memory device of claim 13 , wherein:

a first subset of the memory stack structures is located in a first portion of a memory array region in which each layer of the first-tier alternating stack and each layer of the second-tier alternating stack are present;

a second subset of the memory stack structures is located in a second portion of the memory array region in which each layer of the first-tier alternating stack and each layer of the second-tier alternating stack is present;

the second portion of the memory array region is laterally spaced from the first portion of the memory array region along a first horizontal direction; and

the first dielectric moat structure, the plurality of dielectric pillar structures, the at least one through-memory-level interconnection via structure, and the support pillar structures are located in an intermediate portion of the memory array region located between the first portion of the memory array region and the second portion of the memory array region.