Semiconductor device and method for manufacturing semiconductor device
A manufacturing method of a semiconductor device in which the threshold is adjusted to an appropriate value is provided. The semiconductor device includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is sandwiched, an electron trap layer between the first gate electrode and the semiconductor, and a gate insulating layer between the second gate electrode and the semiconductor. By keeping a potential of the first gate electrode higher than a potential of the source or drain electrode for 1 second or more while heating, electrons are trapped in the electron trap layer. Consequently, threshold is increased and Icut is reduced.
1. A semiconductor device comprising:
a first gate electrode;
an electron trap layer comprising a projection over the first gate electrode;
a first oxide semiconductor over the projection;
a second oxide semiconductor over and in direct contact with the first oxide semiconductor;
a source electrode and a drain electrode in direct contact with a top surface of the second oxide semiconductor;
a third oxide semiconductor over and in direct contact with the second oxide semiconductor;
a gate insulating layer over the third oxide semiconductor;
a second gate electrode over the gate insulating layer; and
an oxide insulating layer over the second gate electrode,
wherein the electron trap layer comprises a first insulating layer which is in direct contact with the source electrode and the drain electrode,
wherein the projection comprises a second insulating layer,
wherein the second insulating layer comprises hafnium oxide or aluminum oxide,
wherein the third oxide semiconductor is in direct contact with a side surface of the projection, a side surface of the first oxide semiconductor, and a side surface of the second oxide semiconductor,
wherein the second gate electrode faces the top surface of the second oxide semiconductor and the side surface of the second oxide semiconductor with the third oxide semiconductor and the gate insulating layer interposed between the second gate electrode and the second oxide semiconductor, and
wherein the oxide insulating layer is in direct contact with a side surface of the third oxide semiconductor, a side surface of the gate insulating layer, and a side surface of the second gate electrode.
2. The semiconductor device according to claim 1 , wherein the third oxide semiconductor is over and in direct contact with the source electrode and the drain electrode.
3. The semiconductor device according to claim 1 , wherein each of the first oxide semiconductor, the second oxide semiconductor, and the third oxide semiconductor comprises indium, gallium, and zinc.
4. The semiconductor device according to claim 1 , wherein an electron affinity of the second oxide semiconductor is higher than an electron affinity of the first oxide semiconductor.
5. The semiconductor device according to claim 1 , wherein a thickness of the second oxide semiconductor is larger than a thickness of the first oxide semiconductor and a thickness of the third oxide semiconductor.
6. The semiconductor device according to claim 1 ,
wherein a band gap of the first insulating layer is larger than a band gap of the second insulating layer.
7. The semiconductor device according to claim 1 , wherein each of the source electrode and the drain electrode comprises ruthenium.
8. The semiconductor device according to claim 1 , wherein the side surface of the second gate electrode, the side surface of the gate insulating layer, and the side surface of the third oxide semiconductor are coplanar with each other.
9. The semiconductor device according to claim 1 , wherein the third oxide semiconductor is in direct contact with the first insulating layer and is extending along the first gate electrode with the first insulating layer interposed between the third oxide semiconductor and the first gate electrode.
10. The semiconductor device according to claim 1 , wherein the oxide insulating layer is in direct contact with the first insulating layer.
11. A semiconductor device comprising:
a first gate electrode;
a layer comprising a projection over the first gate electrode;
a first oxide semiconductor over the projection;
a second oxide semiconductor over and in direct contact with the first oxide semiconductor;
a source electrode and a drain electrode in direct contact with a top surface of the second oxide semiconductor;
a third oxide semiconductor over and in direct contact with the second oxide semiconductor;
a gate insulating layer over the third oxide semiconductor;
a second gate electrode over the gate insulating layer; and
an oxide insulating layer over the second gate electrode,
wherein the layer comprises a first insulating layer which is in direct contact with the source electrode and the drain electrode,
wherein the projection comprises a second insulating layer and a third insulating layer over the second insulating layer,
wherein the second insulating layer comprises hafnium oxide,
wherein the third insulating layer comprises silicon and oxygen,
wherein the third oxide semiconductor is in direct contact with a side surface of the second insulating layer, a side surface of the third insulating layer, a side surface of the first oxide semiconductor, and a side surface of the second oxide semiconductor,
wherein the second gate electrode faces the top surface of the second oxide semiconductor and the side surface of the second oxide semiconductor with the third oxide semiconductor and the gate insulating layer interposed between the second gate electrode and the second oxide semiconductor, and
wherein the oxide insulating layer is in direct contact with a side surface of the third oxide semiconductor, a side surface of the gate insulating layer, and a side surface of the second gate electrode.
12. The semiconductor device according to claim 11 , wherein the third oxide semiconductor is over and in direct contact with the source electrode and the drain electrode.
13. The semiconductor device according to claim 11 , wherein each of the first oxide semiconductor, the second oxide semiconductor, and the third oxide semiconductor comprises indium, gallium, and zinc.
14. The semiconductor device according to claim 11 , wherein an electron affinity of the second oxide semiconductor is higher than an electron affinity of the first oxide semiconductor.
15. The semiconductor device according to claim 11 , wherein a thickness of the second oxide semiconductor is larger than a thickness of the first oxide semiconductor and a thickness of the third oxide semiconductor.
16. The semiconductor device according to claim 11 , wherein the first insulating layer comprises silicon and oxygen.
17. The semiconductor device according to claim 11 , wherein each of the source electrode and the drain electrode comprises ruthenium.
18. The semiconductor device according to claim 11 , wherein the side surface of the second gate electrode, the side surface of the gate insulating layer, and the side surface of the third oxide semiconductor are coplanar with each other.
19. The semiconductor device according to claim 11 , wherein the third oxide semiconductor is in direct contact with the first insulating layer and is extending along the first gate electrode with the first insulating layer interposed between the third oxide semiconductor and the first gate electrode.
20. The semiconductor device according to claim 11 , wherein the oxide insulating layer is in direct contact with the first insulating layer.